 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| port synchronizer for ieee 1588 and 10g/40g /100g synchronous ethernet 82p33741 data sheet version 6
disclaimer integrated device technology, inc. reserves the right to make changes to its products or specifications at any time, without no tice, in order to improve design or performance and to supply the best pos- sible product. idt does not assume any res ponsibility for use of any circuitry described other than the circuitry embodied in a n idt product. the company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent, patent rights or other rights, of integrated device technology, inc. life support policy integrated device technology's products ar e not authorized for use as critical com ponents in life support devices or systems un less a specific written agr eement pertaining to such intended use is exe- cuted between the manufacture r and an officer of idt. 1. life support devices or systems are devices or systems whic h (a) are intended for surgical implant into the body or (b) supp ort or sustain life and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any components of a life support device or system whose fa ilure to perform can be reasonably expecte d to cause the failure of the life suppor t device or system, or to affect its safety or effectiveness. 3 ?2016 integrated device technology, inc. revision 6, july 21, 2016 82p33741 datasheet highlights ............... ................ ................. .............. .............. .............. ............... ............ ................ .............. .............. .......... 5 features ............. ................. ................ ................. .............. .............. .............. .............. ................. .............. .............. .......... 5 applications........... ................ ................. .............. .............. .............. ............... .............. .............. .............. .............. .......... 5 description............. ................ ................. .............. .............. .............. ............... ............. .................... .............. ............ ....... 6 functional block diagram ............... ................ ................. .............. .............. .............. ............. ............. ............... ....... 7 1 pin assignment ....... ................ ................. .............. .............. .............. ............... .............. ................ ................. ............. 8 2 pin description ........... ................ ................. ................ ................. ................ ................. ................ ................. ............. 9 2.1 recommendations for unused input and output pins ........................................................................... ................................ 12 2.1.1 inputs ................................................................................................................... ........................................................................... 12 2.1.2 outputs .................................................................................................................. ......................................................................... 12 2.2 reset operation ............................................................................................................ ......................................................................... 13 3 functional description ............... ................ ................. .............. .............. .............. ............. ............. ............ ......... 14 3.1 hardware functional description ............................................................................................ .................................................... 14 3.1.1 system clock ............................................................................................................. ..................................................................... 14 3.1.2 modes of operation ....................................................................................................... ................................................................. 14 3.1.2.1 dpll1 and dpll2 operating mode ......................................................................................... ........................................ 14 3.1.2.2 dpll3 operating mode .................................................................................................. ................................................. 17 3.1.3 input clocks and frame sync .............................................................................................. .......................................................... 18 3.1.3.1 input clock pre-divider ................................................................................................ ..................................................... 18 3.1.3.2 input clock quality monitoring ......................................................................................... ................................................ 19 3.1.3.3 input clock selection .................................................................................................. ...................................................... 21 3.1.4 dpll locking process ..................................................................................................... ............................................................. 23 3.1.4.1 fast loss .............................................................................................................. ............................................................ 23 3.1.4.2 coarse phase loss ...................................................................................................... .................................................... 23 3.1.4.3 fine phase loss ........................................................................................................ ....................................................... 23 3.1.4.4 hard limit exceeding ................................................................................................... .................................................... 23 3.1.4.5 locking status ......................................................................................................... ......................................................... 24 3.1.4.6 phase lock alarm ....................................................................................................... ..................................................... 24 3.1.5 apll1 and apll2 .......................................................................................................... ................................................................ 24 3.1.6 apll3 .................................................................................................................... .......................................................................... 25 3.1.6.1 external crystals ...................................................................................................... ........................................................ 25 3.1.7 output clocks & frame sync signals ....................................................................................... ................................................... 26 3.1.7.1 output clocks .......................................................................................................... ......................................................... 26 3.1.7.2 frame sync signals ..................................................................................................... .................................................... 27 3.1.8 input and output phase control ........................................................................................... ......................................................... 28 3.1.8.1 dpll1 and dpll2 phase offset control ................................................................................... ........................................ 28 3.1.8.2 input phase control .................................................................................................... ...................................................... 28 3.1.8.3 output phase control ................................................................................................... ..................................................... 28 4 power supply filtering techniques .............. ................. ................. ................ .............. .............. ............ ......... 29 5 microprocessor interface ............. ................ ................. .............. .............. .............. ............. ............... .............. 31 5.1 i2c slave mode ............................................................................................................. ............................................................................ 31 5.1.1 i2c device address ....................................................................................................... ................................................................. 31 5.1.2 i2c bus timing ........................................................................................................... .................................................................... 31 5.1.3 supported tr ansactions ................................................................................................... ............................................................. 33 5.2 i2c master mode ............................................................................................................ ......................................................................... 33 5.2.1 i2c boot-up initialization mode .......................................................................................... ........................................................... 34 5.2.2 eeprom memory map notes .................................................................................................. ...................................................... 34 6 jtag ........... ................. ................ ................. ................ ................. .............. ............. ............... ............... .............. ........... 35 7 thermal management ......... ................. ................ ................. ................. ................ ............... ............. ............ ......... 36 7.1 junction temperature ....................................................................................................... ................................................................. 36 7.2 thermal release path ....................................................................................................... .................................................................. 36 4 ?2016 integrated device technology, inc. revision 6, july 21, 2016 82p33741 datasheet 8 electrical specifications ............ ................. .............. .............. .............. .............. ............... ........... ............ ......... 37 8.1 absolute maximum rating .................................................................................................... .............................................................. 37 8.2 recommended operation conditions ........................................................................................... ................................................. 37 8.3 i/o specifications ......................................................................................................... .......................................................................... 38 8.3.1 cmos input / output port ................................................................................................. ............................................................. 38 8.3.2 lvpecl / lvds input / output port ........................................................................................ ...................................................... 39 8.3.2.1 pecl input port ........................................................................................................ ....................................................... 39 8.3.2.2 lvpecl output port ................................................................................................. ................................................... 40 8.3.3 lvds input / ou tput port ................................................................................................. .............................................................. 41 8.3.3.1 lvds input port ........................................................................................................ ....................................................... 41 8.3.3.2 lvds output port ....................................................................................................... ...................................................... 42 8.3.4 output clock duty cycle .................................................................................................. ............................................................. 43 8.3.5 wiring the differen tial input to accept single-ended levels 44 8.4 jitter performance ........................................................................................................ .................................................................... 45 8.5 input / output clock timing ................................................................................................ ............................................................... 56 8.6 output / output clock timing ............................................................................................... ............................................................ 57 package dimensions ......... ................ ................. ................. ................ ................. ................ ................. .............. .......... 58 ordering information........ ................. ................ ................. ................ ................. ................ ............... .............. .......... 60 revision history ....... ................. ................. .............. .............. .............. .............. .............. ................. ................ ............. 60 5 ?2016 integrated device technology, inc. revision 6, july 21, 2016 highlights ? dpll1 and dpll2 can be used on line cards to manage the genera- tion of synchronous port clocks and ieee 1588 synchronization sig- nals based on multiple system backplane references ? dpll3 can be used on line cards to select incoming line clocks for use on system backplanes; it can also be used for general purpose timing applications ? apll1 and apll2 generate clocks with jitter < 1 ps rms (12 khz to 20 mhz) for: 1000base-t and 1000base-x ports and to generate ieee 1588 time stamp clocks and 1 pulse per second (pps) signals ? apll3 is voltage controlled crys tal oscillator (vcxo) based and generates clocks with jitter <0.3 ps rms (10 khz to 20 mhz) for: 10gbase-r, 10gbase-w, 40gbase-r and 100gbase-r ? fractional-n input dividers suppor t a wide range of reference fre- quencies ? dplls, apll1 and apll2 can be configured from an external eeprom after reset features ? differential reference inputs (in1 to in6) accept clock frequencies between 2 khz and 650 mhz ? single ended inputs (in7 to in12) accept reference clock frequencies between 2 khz and 162.5 mhz ? loss of signal (los) pins (los0 to los3) can be assigned to any clock reference input ? reference monitors qualify/disqua lify references depending on activ- ity, frequency and los pins ? automatic reference selection state machines select the active refer- ence for each dpll based on the reference monitors, priority tables, revertive and non-revertive settings and other programmable settings ? fractional-n input dividers enable the dplls to lock to a wide range of reference clock frequencies including: 10/100/1000 ethernet, 10g/ 40g/100g ethernet, otn, sone t/sdh, pdh, tdm, gsm and gnss frequencies ? any reference inputs (in1 to in12) can be designated as external sync pulse inputs (1 pps, 2 khz, 4 khz or 8 khz) associated with a selectable reference clock input ? frsync_8k_1pps and mfrsync_2k_1pps output sync pulses that are aligned with the selected ex ternal input sync pulse input and frequency locked to the associated reference clock input ? dpll1 and dpll2 can be configured with bandwidths between 18 hz and 567 hz ? dpll1 and dpll2 lock to input references with frequencies between 2 khz and 650 mhz ? dpll3 locks to input references with frequencies between 8 khz and 650 mhz ? dpll1 and dpll2 generate clocks with pdh, tdm, gsm, cpri/ obsai, 10/100/1000 ethernet and gn ss frequencies; these clocks are directly available on out1 ? dpll3 generates n x 8 khz clocks up to 100 mhz that are output on out8 and out9 ? apll1, apll2 and apll3 can be connected to dpll1 and dpll2 ? apll1 and apll2 generate 10/100/1000 ethernet, 10g ethernet, or sonet/sdh frequencies ? apll3 generates 10g/40g/100g ethernet, wan-phy and lan-phy frequencies ? any of eight common tcxo/ocxo frequencies can be used for the system clock: 10 mhz, 12.8 mhz, 13 mhz, 19.44 mhz, 20 mhz, 24.576 mhz, 25 mhz or 30.72 mhz ? the i2c slave interface can be used by a host processor to access the control and status registers ? the i2c master interface can aut omatically load a device configura- tion from an external eeprom after reset; apll3 must be config- ured via the i2c slave interface ? differential outputs out3 to out6 output clocks with frequencies between 1 pps and 650 mhz ? differential outputs out10 and ou t11 output clocks with frequen- cies up to 650 mhz ? single ended outputs out1, out2, and out7 output clocks with fre- quencies between 1 pps and 125 mhz ? single ended outputs out8 and out9 output clocks n*8khz multi- ples up to 100 mhz ? dpll1 and dpll2 support independent programmable delays for each of in1 to in12; the delay for each input is programmable in steps of 0.61 ns with a range of ~78 ns ? the input to output phase delay of dpll1 and dpll2 is programma- ble in steps of 0.0745 ps with a total range of 20 ? s ? the clock phase of each of the output dividers for out1 to out7 is individually programmable in steps of ~200 ps with a total range of +/ -180 ? 1149.1 jtag boundary scan ? 144-pin cabga green package applications ? synchronous clock generation for 10/40g and lower rate, ethernet, pon olt and sonet/sdh line card ? access routers, edge routers, core routers ? carrier ethernet switches ? multiservice access platforms ?pon olt ? lte enodeb port synchronizer for ieee 1588 and 10g/ 40g/ 100g synchr onous ethernet 82p33741 datasheet 6 ?2016 integrated device technology, inc. revision 6, july 21, 2016 82p33741 datasheet description the 82p33741 port synchronizer for ieee 1588 and 10g/40g synchron ous ethernet provides tools to manage timing references, clock conver- sion and timing paths for ieee 1588 and synchr onous ethernet (synce). the device suppor ts up to three independent timing paths for: ieee 1588 clock generation; synce clock generation; and general purpose freq uency translation. the device outputs low-jitter clocks that can directly synchro- nize 100gbase-r, 40gbase-r, 10gbase-r and 10gba se-w and lower-rate ethernet interfaces; as well as cpri/obsai, sonet/sdh and pd h interfaces and ieee 1588 time stamp units (tsus). the 82p33741 accepts six differential reference inputs and six single ended reference inputs that can operate at common etherne t, sonet/sdh and pdh frequencies that range from 2 khz to 650 mhz. the referenc es are continually monitored for loss of signal and for frequ ency offset per user programmed thresholds. all of the references are available to all three digital plls (dplls). the active reference for each dpl l is determined by forced selection or by automatic selection based on user progr ammed priorities, locking allowanc es, reference monitors, and los inputs. the 82p33741 can accept a clock reference and an associated phase lo cked sync signal as a pair. dpll1/dpll2 can lock to the clo ck reference and align the frame sync and multi-frame sync outputs with the paired sync input. the dev ice allows any of the differential or single ended reference inputs to be configured as sync inputs that can be associated with any of the other differentia l or single ended reference inpu ts. the input sync signals can have a frequency of 1 pps, 2 khz, 4khz or 8 khz. this feature enables dpll1/dpll2 to phase align its frame sync and multi-f rame sync outputs with a sync input without the need use a low bandwidth setting to lock directly to the sync input. the dplls support three primary operating m odes: free-run, locked and holdover. in free- run mode the dplls synthesize clocks ba sed on the system clock alone. in locked mode the dplls filter reference clock jitter with the selected bandwidth. in locked mode, the long-term output fre- quency accuracy is the same as the long term frequency accuracy of the selected input reference. in holdover mode, the dpll use s frequency data acquired while in locked mode to generate accurate fr equencies when input refer ences are not available. the 82p33741 requires a system clock for its re ference monitors and other digital circuitry. the fr equency accuracy of the syst em clock deter- mines the frequency accuracy of the dplls in free-run mode. the frequency stability of the system clock determines the frequenc y stability of the dplls in free-run mode and in holdover mode; and it a ffects the wander generation of the dplls in locked mode. dpll1 and dpll2 can be configured with a range of selectable filter ing bandwidths from 18 hz to 567 hz. dpll3 is a wideband (bw > 25hz) fre- quency translator that can be used, for example, to conver t a recovered synce clock to a 25mhz backplane clock. clocks generated by dpll1 and dpll2 can be passed through apll1 or apll2 which are lc based jitter attenuating analog plls (apl ls). the output clocks generated by apll1 and apll2 are suitable for serial gbe and lower rate interfaces, and for ieee 1588 time stamps clocks and 1 pps signals. clocks generated by dpll1 and dpll2 can be pass ed through apll3 which is a voltage controlled crystal oscillator (vcxo) based j itter attenu- ating apll. apll3 can be provisioned with one or two selectable crystal resonators to support up to two base frequencies. the o utput clocks gener- ated by apll3 are suitable for serial 10 gbe and lower rate interfaces. all 82p33741 control and status registers are accessed through an i2c slave microprocesso r interface. for configuring the dplls , apll1 and apll2, the i2c master interface can automatically load a configur ation from an external eeprom after reset. apll3 must be confi gured via the i2c slave interface. 7 ?2016 integrated device technology, inc. revision 6, july 21, 2016 82p33741 datasheet functional block diagram figure 1. functional block diagram control and status registers outdiv outdiv i2c slave jtag i2c master reference monitors reference selection frac-n input dividers sys pll dpll2 apll1 apll2 outdiv outdiv outdiv dpll1 out3p/n out4p/n out5p/n out6p/n out7 system clock los0 / xo_freq0 los1 / xo_freq1 los2 / xo_freq2 los3 ex_sync module in3(p/n) in4(p/n) in5(p/n) in1(p/n) in2(p/n) in6(p/n) in7 in8 in9 in10 in11 in12 frsync_8k_1pps mfrsync_2k_1pps crystal outdiv out1 outdiv out2 outdiv outdiv out10p/n out11p/n apll3 (vcxo) outdiv outdiv out8 out9 dpll3 8 ?2016 integrated device technology, inc. revision 6, july 21, 2016 82p33741 datasheet 1 pin assignment figure 2. pin assignment (top view) 123456789101112 a out5_pos out5_neg out6_pos out6_neg vddao out11_pos vddao ? out10_pos cap2 xtal2_in sonet/sdh/lo s3 xtal1_in a b vssao vddao vddao vssao vssao out11_neg vssao out10_neg vssa xtal2_out mpu_mode1/i 2cm_scl xtal1_out b c vdda vssa vss out7 i2c_sda vdda vdda ic cap1 ic mpu_mode0/i 2cm_sda mfrsync_2 k_1pps c d vssa vdda vsscom vssd vddd vssa vssa cap3 i2c_ad2 i2c_scl out9 out8 d e osci vssa ic vdddo i2c_ad1 vddd0 vssdo vssa dpll3_lock in12 in11 frsync_8k_ 1pps e f tms vdda vssa vssdo vss vssd vddd vssa vdda in10 in6_neg in6_pos f g tck vdda ic vss vss vss ic vss dpll2_lock in9 in5_neg in5_pos g h xo_freq0/ los0 vdda vssa vss vss vss vss vss dpll1_lock in8 vssd vddd_1_8 h j xo_freq1/ los1 xo_freq2/ los2 vss vss vss vss vss vss int_req in7 in4_neg in4_pos j k vdda vdda trstb vssao out2 rstb vssdo ic ic ic in3_neg in3_pos k l vssa vssa tdi vddao tdo ic vdddo out1 vssd vddd_1_8 in2_neg in2_pos l m out4_pos out4_neg vssao vddao out3_pos out3_neg vssdo vdddo ic ic in1_neg in1_pos m 123456789101112 9 ?2016 integrated device technology, inc. revision 6, july 21, 2016 82p33741 datasheet 2 pin description table 1: pin description pin no. name i/o type description global control signal e1 osci i cmos osci: crystal oscillator system clock a clock provided by a crystal oscillator is input on this pin. it is the system clock for the device. the oscillator frequency is selected via pins xo_freq0 ~ xo_freq3. a11 sonet/sdh/ los3 i pull-down cmos sonet/sdh: sonet / sdh frequency selection during reset, this pin determines the default value of the in_sonet_sdh bit (b2, 09h): high: the default value of the in_sonet_sdh bit is ?1? (sonet); low: the default value of the in_sonet_sdh bit is ?0? (sdh). after reset, the value on this pin takes no effect. los3- this pin is used to disqualify input clocks. see input clocks section for more details. k6 rstb i pull-up cmos rstb: reset refer to section 2.2 reset operation for detail. h1 j1 j2 xo_freq0/ los0 xo_freq1/ los1 xo_freq2/ los2 i pull-down cmos xo_freq0 ~ xo_freq2: these pins set the oscillator frequency. xo_freq[2:0] oscillator frequency (mhz) 000 10.000 001 12.800 010 13.000 011 19.440 100 20.000 101 24.576 110 25.000 111 30.720 los0 ~ los2 - these pins are used to disqualify input clocks. see input clocks section for more details. input clock and frame synchronization input signal m12 m11 in1_pos in1_neg i pecl/lvds in1_pos / in1_neg: positive / negative input clock 1 this pin can also be used as a sync input, and in this case a 2 khz, 4 khz, 8 khz, or 1pps signal can be input on this pin. l12 l11 in2_pos in2_neg i pecl/lvds in2_pos / in2_neg: positive / negative input clock 2 this pin can also be used as a sync input, and in this case a 2 khz, 4 khz, 8 khz, or 1pps signal can be input on this pin. k12 k11 in3_pos in3_neg i pecl/lvds in3_pos / in3_neg: positive / negative input clock 3 this pin can also be used as a sync input, and in this case a 2 khz, 4 khz, 8 khz, or 1pps signal can be input on this pin. j12 j11 in4_pos in4_neg i pecl/lvds in4_pos / in4_neg: positive / negative input clock 4 this pin can also be used as a sync input, and in this case a 2 khz, 4 khz, 8 khz, or 1pps signal can be input on this pin. g12 g11 in5_pos in5_neg i pecl/lvds in5_pos / in5_neg: positive / negative input clock 5 this pin can also be used as a sync input, and in this case a 2 khz, 4 khz, 8 khz, or 1pps signal can be input on this pin. f12 f11 in6_pos in6_neg i pecl/lvds in6_pos / in6_neg: positive / negative input clock 6 this pin can also be used as a sync input, and in this case a 2 khz, 4 khz, 8 khz, or 1pps signal can be input on this pin. j10 in7 i pull-down cmos in7: input clock 7 this pin can also be used as a sync input, and in this case a 2 khz, 4 khz, 8 khz, or 1pps signal can be input on this pin. h10 in8 i pull-down cmos in8: input clock 8 this pin can also be used as a sync input, and in this case a 2 khz, 4 khz, 8 khz, or 1pps signal can be input on this pin. g10 in9 i pull-down cmos in9: input clock 9 this pin can also be used as a sync input, and in this case a 2 khz, 4 khz, 8 khz, or 1pps signal can be input on this pin. 10 ?2016 integrated device technology, inc. revision 6, july 21, 2016 82p33741 datasheet f10 in10 i pull-down cmos in10: input clock 10 this pin can also be used as a sync input, and in this case a 2 khz, 4 khz, 8 khz, or 1pps signal can be input on this pin. e11 in11 i pull-down cmos in11: input clock 11 this pin can also be used as a sync input, and in this case a 2 khz, 4 khz, 8 khz, or 1pps signal can be input on this pin. e10 in12 i pull-down cmos in12: input clock 12 this pin can also be used as a sync input, and in this case a 2 khz, 4 khz, 8 khz, or 1pps signal can be input on this pin. output frame synchronization signal e12 frsync _8k_1pps ocmos frsync_8k_1pps: 8 khz frame sync output an 8 khz signal or a 1pps sync signal is output on this pin. c12 mfrsync _2k_1pps ocmos mfrsync_2k_1pps: 2 khz mu ltiframe sync output a 2 khz signal or a 1pps sync signal is output on this pin. output clock l8 k5 out1 out2 ocmos out1 ~ out2: output clock 1 ~ 2 m5 m6 out3_pos out3_neg o pecl/lvds out3_pos / out3_neg: positive / negative output clock 3 the lvds output has internal 100 ohm termination. m1 m2 out4_pos out4_neg o pecl/lvds out4_pos / out4_neg: positive / negative output clock 4 the lvds output has internal 100 ohm termination. a1 a2 out5_pos out5_neg o pecl/lvds out5_pos / out5_neg: positive / negative output clock 5 the lvds output has internal 100 ohm termination. a3 a4 out6_pos out6_neg o pecl/lvds out6_pos / out6_neg: positive / negative output clock 6 the lvds output has internal 100 ohm termination. c4 out7 o cmos out7: output clock 7 d12 out8 o cmos out8: output clock 8 d11 out9 o cmos out9: output clock 9 a8 b8 out10_pos out10_neg o pecl out10_pos / out10_neg: positive / negative output clock 10 a6 b6 out11_pos out11_neg o pecl out11_pos / out11_neg: positive / negative output clock 11 miscellaneous c9, a9, d8 cap1, cap2, cap3 cap1, cap2 and cap3: analog power filter capacitor connection 1 to 3. these capacitors are be part of the power filtering. a12 xtal1_in i analog crystal oscillator 1 input. determines first of two frequency families (sonet/sdh, ethernet or ethernet*66/64) available for apll3. connect to ground if xtal1 is not used. b12 xtal1_out o analog crystal oscillator 1 output. leave open if xtal1 is not used. a10 xtal2_in i analog crystal oscillator 2 input. determines first of two frequency families (chosen from sonet/sdh, ethernet or ethernet*66/ 64) available for apll3. connect to ground if xtal2 is not used b10 xtal2_out o analog crystal oscillator 2 output. leave open if xtal2 is not used. lock signal e9 dpll3_lock ocmos dpll3_lock this pin goes high when dpll3 is locked table 1: pin descrip tion (continued) pin no. name i/o type description 11 ?2016 integrated device technology, inc. revision 6, july 21, 2016 82p33741 datasheet g9 dpll2_lock ocmos dpll2_lock this pin goes high when dpll2 is locked h9 dpll1_lock ocmos dpll1_lock this pin goes high when dpll1 is locked microprocessor interface j9 int_req o tri-state cmos int_req: interrupt request this pin is used as an interrupt request. the output characteristics are determined by the hz_en bit (b1, 0ch) and the int_pol bit (b0, 0ch). b11 c11 mpu_mode1/ i2cm_scl mpu_mode0/ i2cm_sda i/o pull-up cmos/ open drain mpu_mode[1:0]: microprocessor interface mode selection during reset, these pins determine the default value of the mpu_sel_cnfg[1:0] bits as fol- lows: 00: i2c mode 01 ~ 10: reserved 11: eeprom mode i2cm_scl: serial clock line in i2c master mode, the serial clock is output on this pin. i2cm_sda: serial data input for i2c master mode in i2c master mode, this pin is used as the for the serial data. d9 i2c_ad2 i pull-down cmos i2c_ad2: device address bit 2 i2c_ad[2:1] pins are the address bus of the microprocessor interface. e5 i2c_ad1 i pull-down cmos i2c_ad1: device address bit 1 2c_ad[2:1] pins are the address bus of the microprocessor interface. d10 i2c_scl i pull-down cmos i2c_scl: serial clock line the serial clock is input on this pin. c5 i2c_sda i/o pull-up open drain i2c_sda: serial data input/output this pin is used as the input/output for the serial data. jtag (per ieee 1149.1) f1 tms i pull-up cmos tms: jtag test mode select the signal on this pin controls the jtag test performance and is sampled on the rising edge of tck. k3 trstb i pull-up cmos trst: jtag test reset (active low) a low signal on this pin resets the jtag test port. this pin should be connected to ground when jtag is not used. g1 tck i pull-down cmos tck: jtag test clock the clock for the jtag test is input on this pin. tdi and tms are sampled on the rising edge of tck and tdo is updated on the falling edge of tck. if tck is idle at a low level, all stored-state devices contained in the test logic will indefinitely retain their state. l3 tdi i pull-up cmos tdi: jtag test data input the test data are input on this pin. they are clocked into the device on the rising edge of tck. l5 tdo o tri-state cmos tdo: jtag test data output the test data are output on this pin. they are clocked out of the device on the falling edge of tck. tdo pin outputs a high impedance signal except during the process of data scanning. power & ground c1, c6, c7, d2, f2, f9, g2, h2, k1, k2 vdda power - vdda : analog core power - +3.3v dc nominal a5, a7, b2, b3, l4, m4 vddao power vddao : analog output power - +3.3v dc nominal e4, e6, l7, m8 vdddo power vdddo : digital output power - +3.3v dc nominal d5, f7 vddd power vddd : digital core power - +3.3v dc nominal table 1: pin descrip tion (continued) pin no. name i/o type description 12 ?2016 integrated device technology, inc. revision 6, july 21, 2016 82p33741 datasheet 2.1 recommendations for unused input and output pins 2.1.1 inputs control pins all control pins have internal pul l-ups or pull-downs ; additional resis- tance is not required but can be added for additional protection. a 1k resistor can be used. single-ended clock inputs for protection, unused single- ended clock inputs should be tied to ground. differential clock inputs for applications not requiring the use of a differential input, both *_pos and *_neg can be left floating. though not required, but for additional protection, a 1k resistor can be tied from _pos to ground. xtal inputs for applications not requiring the use of a crystal oscillator input, both _in and _out can be left floating. though not required, but for additional protection, a 1k resistor can be tied from _in to ground. 2.1.2 outputs status pins for applications not requiring the use of a status pin, we recommend bringing out to a test point for debugging purposes. single-ended clock outputs all unused single-ended clock outputs can be left floating, or can be brought out to a test point for debugging purposes. differential clock outputs all unused differential outputs can be left floating. we recommend that there is no trace attached. both sides of the differential output pair should either be left floating or terminated. l10, h12 vddd_1_8 power vddd_1_8 : digital core power - +1.8v dc nominal b9, c2, d1, d6, d7, e2, e8, f3, f8, h3, l1, l2 vssa ground - vssa : ground b1, b4, b5, b7, k4, m3 vssao ground vssao : ground e7, f4, k7, m7 vssdo ground vssdo : ground d4, f6, h11, l9 vssd ground vssd : ground d3 vsscom ground - vsscom: ground c3, f5, g4, g5, g6, g8, h4, h5, h6, h7, h8, j3, j4, j5, j6, j7, j8 vss ground - vss : ground other c8, c10, e3, g3, g7, k8 k9, k10, l6, m9, m10 ic - - ic : internal connection internal use. this pin must be left open for normal operation. table 1: pin descrip tion (continued) pin no. name i/o type description 13 ?2016 integrated device technology, inc. revision 6, july 21, 2016 82p33741 datasheet 2.2 reset operation the device must be reset properly in order to ensure operations confor m with specification. to properly reset the device, the rstb pin must be held at a low value for at least 50 usec. the device should be brought out o f reset only at the time when power supplies are stabilized and the system clock is av ailable on osci pin. the rstb can be held low until this time , or pulsed low for at least 50us after this time. the bootstrap pins (xo_freq[2:0], mpu_mode[1 :0], i2c_ad[2:1], sonet/sdh) need to be held at desired states for at least 2ms aft er de- assertion of rstb pin to allow correct sampling. see figure 3 for detail. if loading from an eeprom, the maximum time from rstb de-assert to have stable clocks is 100ms. note that if there is a bad eep rom read sequence and the eeprom loading is repeated once or twice (three times halts the device), then this time can be 2 or 3 times lo nger respectively. if not loading from eeprom the maximum time from rstb de-assert to have stable clocks is 10ms. an on-board reset circuit or a commercially available voltage s upervisory can be used to generate the reset signal. it is also feasible to use a standalone power-up rc reset circuit. when usi ng a power-up rc reset circuit, careful c onsideration must be taken into account to fine tune the circuit properly based on each pow er supply's specification to ens ure the power supply rise time is fast enough with respect t o the rc time constant of the rc circuit. figure 3. reset timing diagram vddd vdda osci rstb 50 s 2ms bootstrap pins* * bootstrap pins are: xo_freq[2:0], mpu_mode[1:0], i2c_ad[2:1], sonet/sdh 14 ?2016 integrated device technology, inc. revision 6, july 21, 2016 82p33741 datasheet 3 functional description 3.1 hardware functi onal description 3.1.1 system clock a crystal oscillator should be used as an input on the osci pin. this clock is provided for the device as a system clock. the system clock is used as a reference clock for all the internal circuits. the active edge of the system clock can be selected by the osc_edge bit in xo_freq_cnfg register. eight common oscillator frequencies can be used for the stable sys- tem clock. the oscillator frequency can be set by pins or by xo_fre- q_cnfg register as shown in table 2 . an offset from the nominal frequency may be compensated by set- ting the nominal_freq_value[23:0] bits. the calibration range is within 741 ppm. the crystal oscillator should be chos en accordingly to meet different applications and standard requirements. (see an-807 recommended crystal oscillators for netsynchro wan pll). 3.1.2 modes of operation 3.1.2.1 dpll1 and dpll2 operating mode the dpll1 and dpll2 can operate in several different modes as shown in table 3. the dpll1 and dpll2 operating mode is controlled by the dpll1_operating_mode[3:0] bits and dpll2_operating_- mode[3:0] bits respectively. when the operating mode is switc hed automatically, the operation of the internal state machine is shown in figure 4 . whether the operating mode is under ex ternal control or is switched automatically, the current operating mode is always indicated by the dpll1/2_dpll_operating_sts[3:0] bits. when the operating mode switches, the dpll1/2_operating_st s bit will be set. if the dpll1/ 2_operating_sts bit is ?1?, an interr upt will be generated if the corre- sponding mask bit is set to ?1?, the mask bit is set to ?0? by default. table 2: oscillator frequencies xo_freq[2:0] pins xo_freq_cnfg[2:0] bits oscillator frequency (mhz) 000 10.000 001 12.800 010 13.000 011 19.440 100 20.000 101 24.576 110 25.000 111 30.720 table 3: dpll1/2 operating mode control dpll1/2_operating_mode[3:0 ] dpll1/2 operating mode 0000 automatic 0001 forced - free-run 0010 forced - holdover 0011 reserved 0100 forced - locked 0101 forced - pre-locked2 0110 forced - pre-locked 0111 forced - lost-phase 1000-1111 reserved 15 ?2016 integrated device technology, inc. revision 6, july 21, 2016 82p33741 datasheet figure 4. dpll automatic operating mode notes to figure 4 : 1. reset. 2. an input clock is selected. 3. the dpll selected input clock is disqualified and no qualified input clock is available. 4. the dpll selected input clock is switched to another one. 5. the dpll selected input clock is locked (the dpll_lock bit is ?1?). 6. the dpll selected input clock is disqualified and no qualified input clock is available. 7. the dpll selected input clock is unlocked (the dpll_lock bit is ?0?). 8. the dpll selected input clock is locked again (the dpll_lock bit is ?1?). 9. the dpll selected input clock is switched to another one. 10. the dpll selected input clock is locked (the dpll_lock bit is ?1?). 11. the dpll selected input clock is disqualified and no qualified input clock is available. 12. the dpll selected input clock is switched to another one. 13. the dpll selected input clock is disqualified and no qualified input clock is available. 14. an input clock is selected. 15. the dpll selected input clock is switched to another one. the causes of item 4, 9, 12, 15 - ?the dpll selected input clock is switched to another one? - are: (the dpll selected input clock is dis- qualified and another input clock is switched to) or (in revertive switching, a qualified input clock with a higher priority is switched to) or (the dpll selected input clock is switched to another one forced selec- tion). free-run mode 1 pre-locked mode 2 3 4 locked mode 5 lost-phase mode holdover mode 7 8 pre-locked2 mode 13 14 15 6 12 11 9 10 16 ?2016 integrated device technology, inc. revision 6, july 21, 2016 82p33741 datasheet 3.1.2.1.1 free-run mode in free-run mode, the dpll1/2 output refers to the system clock and is not affected by any input clock. the accuracy of the dpll1/2 out- put is equal to that of the system clock. 3.1.2.1.2 pre-locked mode in pre-locked mode, the dpll1/2 output attempts to track the selected input clock. the pre-locked mode is a secondary, temporary mode. 3.1.2.1.3 locked mode in locked mode, the dpll1/2 is lock ed to the input clock. the phase and frequency offset of the dpll1/2 out put track those of the dpll1/2 selected input clock. for a closed loop, different bandwidths and damping factors can be used. they are set by the dp ll1/2_locked_bw[4:0] bits and the dpll1/2_locked_damping[2:0] bits respectively. dpll1/ 2_locked_bw[4] must be set to 1. the locked bandwidth is selectable can be set as shown in table 4. 3.1.2.1.4 pre-locked2 mode in pre-locked2 mode, the dpll1/2 output attempts to track the selected input clock. the pre-locked2 mode is a secondary, temporary mode. 3.1.2.1.5 lost-phase mode in lost-phase mode, the dpll1/2 output attempts to track the selected input clock. the lost-phase mode is a secondary, temporary mode. 3.1.2.1.6 holdover mode in holdover mode, the dpll1/2 resorts to the stored frequency data acquired in locked mode to control its output. the dpll1/2 output is not phase locked to any input clock. the holdover mode is set to curr ent averaged value with holdover fil- ter bw of ~1.5mhz. in this mode the initial frequency offset is better than 1.1e-5ppm assuming that there is no in-band jitter/wander at the input just before entering holdover state. the offset value can be read from the holdover_freq_cnfg[39:0] bits by setting the read_avg bit to ?1?. the holdover frequency resolution is calculated as follows: holdover frequency resolution: ho_freq_res = (77760/1638400) * 2^-48 the holdover value read from regi ster bits holdover_freq_cnfg[[39:0] must be converted to decimal: ho_value_dec = holdover_freq_cnfg[39:0] value in decimal the frequency offset in ppm is calculated as follows: holdover frequency o ffset (ppm) = (ho_freq_res * ho_value_dec)/ (1-((ho_freq_res * ho_value_dec)/1e6)) 3.1.2.1.7 hitless reference switching bit hitless_switch_en in dpll1/2_m on_sw_pbo_cnfg register can be used to set hitless reference switch ing. when a hitless switching (hs) event is triggered, the phase offset of the selected input clock with respect to the dpll1/2 output is measured. the device then automati- cally accounts for the measured phase offset and compensates for the appropriate phase offset into the dpll output so that the phase tran- sients on the dpll1/2 output are minimized. the input frequencies should be set to frequencies equal to 8khz or higher. if hitless_switch_en is set to ?1?, a hs event is triggered if any one of the following conditions occurs: ? dpll1/2 selected input clock switches to a different reference ? dpll1/2 exits from holdover mode or free-run mode for the two conditions, the phase transients on the dpll1/2 output are minimized to be no more than 0.61 ns with hs. the hs can also be frozen at the current phase offset by setting the hitless_switch_freeze bit in dpll1/2_mon_sw_pbo_cnfg register. when the hs is frozen, the device will ignore any further hs ev ents triggered by the above two con- ditions, and maintain the current phase offset. when the hs is disabled, there may be a phase shift on the dpll1/2 output, as the dpll1/2 output tracks back to 0 degree phase offset with respect to the dpll1/2 selected input clock. this phase shift can be lim- ited; see section 3.1.2.1.8 phase slope limit on page 17 . table 4: dpll1/2 locked bandwidth dpll1/2_locked_bw[3:0] bw 0000 18 hz 0001 35 hz 0010 71 hz 0011 142 hz 0100 283 hz 0101 567 hz 0110-1111 reserved 17 ?2016 integrated device technology, inc. revision 6, july 21, 2016 82p33741 datasheet 3.1.2.1.8 phase slope limit both dpll1 and dpll2 provide a phase slope limiting feature to limit the rate of output phase movement. the limit level is selectable via dpll1/2_ph_limit[1:0] bits in dpll1/ 2_bw_overshoot_cnfg register. the options are shown in table 5 . 3.1.2.1.9 phase and frequency detector pfd output limit the pfd output is limited to be within 1 ui or within the coarse phase limit (refer to chapter 3.1.4.2 ), as determined by the mul- ti_ph_app bit. 3.1.2.1.10 frequency offset limit the dpll1/2 output is limited to be within the programmed dpll hard limit (refer to chapter 3.1.4.4 ). 3.1.2.2 dpll3 operating mode the dpll3 operating mode is controlled by the dpll3_operat- ing_mode[2:0] bits, as shown in table 6 . dpll3 is disabled by default, write ?0? to bit dpll3_dpll_pdn in pdn_conf register to enable it. when the operating mode is switched automatically, the operation of the internal state machine is shown in figure 5 : figure 5. dpll3 automatic operating mode notes to figure 5 : 1. reset. 2. an input clock is selected. 3. (the dpll3 selected input clock is disqualified) or (a qualified input clock with a higher priority is switched to) or (the dpll3 selected input clock is switched to another one by forced selec- tion). 4. an input clock is selected. 5. no input clock is selected. 3.1.2.2.1 free-run mode in free-run mode, the dpll3 output refers to the system clock and is not affected by any input clock. the accuracy of the dpll3 output is equal to that of the system clock. 3.1.2.2.2 locked mode in locked mode, the dpll3 is locked to the input clock. the phase and frequency offset of the dpll3 output track those of the dpll3 selected input clock. dpll3 is a wide bw dpll, with loop bandwidth higher than 25hz. table 5: dpll1/2 phase slope limit dpll1/2_ph_limit[1:0] phase slope limit 00 61s/s (gr-1244 st3) 01 885ns/s (gr-1244-core st2 and 3e, gr-253-core st3 and g.8262 eec option 2) 10 7.5 s/s (g.813 opt1, g.8262 eec- option 1) 11 unlimited / 1.4 ms/s (default) *note: the default phase slope limiting is set to 0 ns/s, therefore, the phase slope limiting must be set to the proper value to meet different standards according to this table. for psl = 885 ns/s, it is recommended that a tcxo be used. table 6: dpll3 operating mode control dpll3_operating_mode[2:0] dpll3 operating mode 000 automatic 001 forced - free-run 010 forced - holdover 100 forced - locked 2 locked mode holdover mode free-run mode 1 3 4 5 18 ?2016 integrated device technology, inc. revision 6, july 21, 2016 82p33741 datasheet 3.1.2.2.3 holdover mode in holdover mode, the dpll3 has 2 modes of operation for the hold- over set by dpll3_auto_avg bit in dpll3_holdover_mode_cnfg regis- ter. dpll3_auto_avg = 0: holdover frequency is the instantaneous value of integral path just before entering holdover. if the dpll3 was locked to an input clock reference that has no in-band jitter/wander and was then manually set to go into holdover, the initial frequency accuracy is 4.4x10-8 ppm. dpll3_auto_avg = 1: averaged frequency value is used as holdover frequency. the holdover average bandwid th is about 1.5mhz. in this mode the initial frequency offset is 1.1e-5ppm assuming that there is no in-band jitter/wander at the input ju st before entering holdover state. 3.1.2.2.4 pfd output limit the pfd output is limited to be within 1 ui or within the coarse phase limit (refer to chapter 3.1.4.2 ), as determined by the mul- ti_ph_app bit. 3.1.2.2.5 frequency offset limit the dpll3 output is limited to be within the dpll hard limit (refer to chapter 3.1.4.4 ). 3.1.3 input clocks and frame sync the 82p33741 has 12 input clocks that can also be used for frame sync pulses. the 82p33741 supports telecom and ethernet frequencies from 1pps up to 650 mhz. any of the input clocks can be used as a frame pulse or sync signal. the sync_sel[3:0] bits in in n _los_sync_cnfg (12 < n < 1) registers sets which pin is used as fram e pulse or sync signal. in1 to in12 can be used for 2 khz, 4 khz or 8 khz frame pulses or 1pps sync signal.the input frequency should match the setting in the sync_freq[1:0] bits in dpll1/2_input_mode_cnfg register. 3.1.3.1 input clock pre-divider each input clock is assigned an inte rnal pre-divider . the pre-divider can be used to divide the clock frequency down to a convenient fre- quency, such as 8 khz for the internal dpll1 and dpll2. note that t1 and e1 references can exhibit subs tantial jitter with frequencies above 4 khz. these references should be applied to dpll1 or dpll2 without being divided down to 8 khz. for in1 ~ in12, the dpll required frequency is set by the corre- sponding in_freq[3:0] bits. each pre-divider consists of an fec divider and a divn divider,. in3~in8 also include an hf (high frequency) divider. figure 6 shows a block diagram of the pre-di viders for an input clock. for 2 khz, 4 khz or 8 khz input clock frequency only, the pre-divider should be bypassed by setting inn_div[1:0] bits = ?0? (1 < n < 6), direct_div bit = ?0?, and lock_8k bit = ?0?. the corresponding in_- freq[3:0] bits should be set to match the input frequency. the hf divider, which is avail able for in1 ~ in6, should be used when the input clock is higher than ( ? ) 162.5 mhz. the input clock can be divided by 4, 5 or can bypass t he hf divider, as determined by the inn_div[1:0] bits (1 < n < 6). the divn divider can be bypas sed, as determined by the direct_div bit and the lock_8k bi t. when divn divider is bypassed, the corresponding in_freq[3:0] bits should be set to match the input frequency. divn must be bypassed on a reference clock input that is also associated with another reference input used as sync. table 7: in_freq[3:0] dpll frequency in_freq[3:0] bits dpll frequency 0000 8 khz 0001 1.544 mhz/ 2.048 mhz (depends on sonet/ sdh bit) 0010 6.48 mhz 0011 19.44 mhz 0100 25.92 mhz 0101 38.88 mhz 0110 - 1000 reserved 1001 2 khz 1010 4 khz 1011 reserved 1100 6.25 mhz 1101 reserved 1110 25 mhz 1111 reserved 19 ?2016 integrated device technology, inc. revision 6, july 21, 2016 82p33741 datasheet when the divn divider is used for inn (1 ? n ? 12), the division factor setting should observe the following order: 1. write the lower eight bits of the division factor to the pre_divn_value[7:0] bits; 2. write the higher eight bits of the division factor to the pre_divn_value[14:8] bits. the division factor is calculated as follows: division factor = (the frequency of the clock input to the divn divider the frequency of the dpll required clock set by the in_- freq[3:0] bits) - 1 the pre-divider configuration and the division factor setting depend on the input clock on one of the in3 ~ in14 pins and the dpll required clock. for the fractional input divider, th e fec divider, each input clock has a 16-bit (fec_divp_cnfg[15:0]) that r epresents the value of the numerator and a 16-bit (fec_divq_cnfg[15:0]) that represents the value of the denominator of fec divider. the fec di vision factor is calculated as fol- lows: fec division factor = (fec_divp_cnfg[15:0]) (fec_divq_cnfg[15:0]) figure 6. pre-divider for an input clock 3.1.3.2 input clock quality monitoring the qualities of all the input clocks are always monitored in the fol- lowing aspects: ? activity ? frequency los monitoring is only conducted on in1 and in2. activity and fre- quency monitoring are conducted on all the input clocks. the qualified clocks are availabl e for selection for all 3 dplls. 3.1.3.2.1 activity monitoring activity is monitored by using an internal leaky bucket accumulator, as shown in figure 7 . each input clock is assigned an internal leaky bucket accumulator. the input clock is monitored for each period of 128 ms, the internal leaky bucket accumulator is increased by 1 when an event is detected; and it is decreased by 1 when no event is det ected within the period set by the decay rate. the event is that an i nput clock drifts outside (>) 500 ppm with respect to the system clock within a 128 ms period. there are four configurations (0 - 3) for a leaky bucket accumulator. the leaky bucket configuration for an input clock is selected by the cor- responding bucket_sel[1:0] bits. ea ch leaky bucket configuration consists of four elements: upper thre shold, lower threshold, bucket size and decay rate. the bucket size is the capability of the accumulator. if the number of the accumulated events reach the bucket size, the accumulator will stop increasing even if further events are detected. the upper threshold is a point above which a no-activity alarm is raised. the lower threshold is a point below which the no-activity alar m is cleared. the decay rate is a certain period during which the accu mulator decreases by 1 if no event is detected. the leaky bucket configuration is programmed by one of four groups of register bits: the bucket_size_n_data[7:0] bits, the upper_ threshold_n_data[7:0] bits, the lower_threshold_n_ data[7:0] bits and the decay_rate_n_d ata[1:0] bits respectively; ?n? is 0 ~ 3. the no-activity alarm status of t he input clock is indicated by the inn_no_activity_alarm bit (12 ? n ? 1). the input clock with a no- activity alarm is disqualified for clock selec- tion for the dplls. hf divider (for in1 ~ in6) divn divider 1< n < 19440 0 1 00 01 fec divider (p/q) dpll clock input clock inn 1 < n < 12 pre-divider inn_div[1:0] bits 1 < n < 6 lock_8k bit direct_div bit 20 ?2016 integrated device technology, inc. revision 6, july 21, 2016 82p33741 datasheet figure 7. input clock activity monitoring 3.1.3.2.2 frequency monitoring frequency is monitored by compari ng the input clock with a refer- ence clock. the reference clock can be derived from the system clock or the output of dpll1, as determined by the freq_mon_clk bit. each reference clock has a hard frequency monitor and a soft fre- quency monitor. both monitors have tw o thresholds, rejecting threshold and accepting threshold, which are set in hard_freq_mon_- threshold[7:0] and soft_freq_mon_threshold[7:0]. so four frequency alarm thresholds are set for frequency monitoring: hard alarm accepting threshold, hard alarm rejecting threshold, soft alarm accepting threshold and soft alarm rejecting threshold. the frequency hard alarm accepting threshold can be calculated as follows: frequency hard alarm accepti ng threshold (ppm) = (hard_fre- q_mon_threshold[7:4] + 1) x freq_mon_factor[3:0] (b3~0, freq_mon_factor_cnfg) the frequency hard alarm rejecting threshold can be calculated as follows: frequency hard alarm rejecti ng threshold (ppm) = (hard_fre- q_mon_threshold[3:0] + 1) x freq_mon_factor[3:0] (b3~0, freq_mon_factor_cnfg) when the input clock frequency rises to above the hard alarm reject- ing threshold, the inn_freq_hard_alarm bit (12 ? n ? 1) will alarm and indicate ?1?. the alarm will remain until the frequency is down to below the hard alarm accepting threshold, then the inn_fre- q_hard_alarm bit will return to ?0 ?. there is a hysteresis between fre- quency monitoring, refer to figure 8. hysteresis frequency monitoring page 21. the soft alarm is indicated by the inn_freq_soft_alarm bit (12 ? n ? 1) in the same way as hard alarm. if the freq_mon_hard_en bit is ?1 ?, the frequency alarm status of the input clock is indicated by the inn_freq_hard_alarm bit (12 ? n ? 1). when the freq_mon_hard_en bit is ?0?, no frequency hard alarm is raised even if the input clock is above the frequency alarm threshold. the input clock with a frequency hard alarm is disqualified for clock selection for the dplls, but the soft alarm doesn?t affect the clock selec- tion for the dplls. the frequency of each input clock with respect to the reference clock can be read by doing the following step: 1. read the value in the in_freq_value[7:0] bits and calculate as follows: input clock frequency (ppm) = in_freq_value[7:0] * fre- q_mon_factor[3:0] note that the value set by the freq_mon_factor[3:0] bits depends on the application. input clock leaky bucket accumulator no-activity alarm indication decay rate bucket size upper threshold lower threshold 0 clock signal with no event clock signal with events 21 ?2016 integrated device technology, inc. revision 6, july 21, 2016 82p33741 datasheet figure 8. hysteresis frequency monitoring 3.1.3.3 input clock selection for dpll1, dpll2 and dpll3, the dpll1/2/3_input_sel[3:0] bits (register dpll1/2/3_input_sel_cnfg) det ermine the input clock selection, as shown in table 8 : 3.1.3.3.1 forced selection in forced selection, the selected input clock is set by the dpll1_in- put_sel[3:0], dpll2_input_sel[3:0], and dpll3_input_sel[4:0] bits. the results of input clocks quality monitoring do not affect the input clock selection if forced selection is used. accepted rejected (alarmed) accepted accepting threshold rejecting threshold table 8: input clock selectio n for dpll1, dpll2 and dpll3 dpll1/2/3 _input_sel[3:0] input clock selection 0000 automatic selection 0001 ~ 1110 forced selection (in1 ~ in14) 1111 reserved 22 ?2016 integrated device technology, inc. revision 6, july 21, 2016 82p33741 datasheet 3.1.3.3.2 automatic selection in automatic selection, the input clock selection is determined by input clock being valid, priority and input clock configuration. the input clock is declared valid depending on the results of input clock quality monitoring (refer to chapter 3.1.3.2 ). the input clock can be configured to be valid and therefore be allowed to participate in the locking process by setting to ?0? the corresponding inn_valid bit (12 ? n ? 1) in dpll_remote_input_valid_cnfg register, by default all the inputs are not valid, and therefore the user must set the corresponding bit to ?0? in order to allow the dpll to lock to a particular input clock. within all the qualified input clocks, the one with the highest priority is selected. the priority is set by the correspondi ng inn_sel_priority[3:0] bits in dpll_inn_sel_priority_cnfg (12 ? n ? 1). if more than one qualified input clock inn is available, then it is important to set appropriate priori- ties to the input clocks, two input cl ocks must not have the same priority. this process is shown in figure 9 . figure 9. qualified input clocks for automatic selection 3.1.3.3.2.1 input clock validation for all the input clocks, the input is declared valid depending on the results of input clock quali ty monitoring (refer to chapter 3.1.3.2 ). the in_noise_window bit should be set to ?1? if any of inn_freq[3:0] is set for frequencies ? 8 khz, by default it is set to ?0?. for dpll1 and dpll2, the following conditions must be satisfied for the input clock to be valid; otherwise, it is invalid. ? no no-activity alarm (the inn_no_activity_alarm bit is ?0?); ? no frequency hard alarm (the inn_freq_hard_alarm bit is ?0?); ? no phase lock alarm, i.e., the inn_ph_lock_alarm bit is ?0?; ? if the ultr_fast_sw bit is ?1?, the dpll selected input clock misses less than (<) 2 consecutive clock cycles; if the ultr_- fast_sw bit is ?0?, this condition is ignored; ? los[3:0] are not set to disqualify the input clock for dpll3, the following conditions must be satisfied for the input clock to be valid; otherwise, it is invalid. ? no no-activity alarm (the inn_no_activity_alarm bit is ?0?); ? no frequency hard alarm (the inn_freq_hard_alarm bit is ?0?); ? los[3:0] are not set to disqualify the input clock the inn bit (12 ? n ? 1) indicates whether or not the clock is valid. when the input clock changes from ?valid ? to ?invalid?, or from ?invalid? to ?valid), the inn bit will be set. if the inn bit is ?1?, an interrupt will be gen- erated. when the dpll selected input clock has failed, i.e., the selected input clock changes from ?valid? to ?invalid?, the dpll_main_ref_- failed bit will be set. if the dpll_main_ref_failed bit is ?1?, an interrupt will be generated. 3.1.3.3.2.2 revertive and non-revertive switching for dpll1 and dpll2, revertive and non-revertive switchings are supported, as selected by the revertive_mode bit. for dpll3, only revertive switching is supported. gr-1244 defines revertive and non- revertive reference switching. in non-revertive switching, a switch to an alternate reference is main- tained even after the original refer ence has recovered from the failure that caused the switch. in revertive switching, the clock switches back to the original reference after that reference recovers from the failure, independent of the condition of the alter nate reference. in non-revertive switching, input clock switch is minimized. in revertive switching, the sele cted input clock is switched when another qualified input clock with a higher priority than the current selected input clock is available. therefore, if revertive_mode bit is set to ?1?, then the selected input clock is switched if any of the following is satisfied: ? the selected input clock is disqualified; ? another qualified input clock with a higher priority than the selected input clock is available. input clock validation priority inn_sel_priority[3:0] '0000' input configuration in n_valid = '0' yes no no no yes yes all qualified input clocks are available for automatic selection input clock quality monitoring (los, activity, frequency) in n = '1' 23 ?2016 integrated device technology, inc. revision 6, july 21, 2016 82p33741 datasheet a qualified input clock with the highest priority is selected by revertive switching. if more than one qualified input clock inn is available, then it is important to set appropriate priori ties to the input clocks, two input clocks must not have the same priority. in non-revertive switching, the dpll1/2 selected input clock is not switched when another qualified input clock with a higher priority than the current selected input clock becom es available. in this case, the selected input clock is switched and a qualified input clock with the high- est priority is selected only when t he dpll1/2 selected input clock is dis- qualified. if more than one qualified input clock inn is available, then it is important to set appropriate prioriti es to the input clocks, two input clocks must not have the same priority. 3.1.3.3.3 selected / qualified input clocks indication the selected input clock is indi cated by the currently_select- ed_input[3:0] bits. when the device is configured in automatic selection and revertive switching is enabled, the input clock indicated by the currently_se- lected_input[3:0] bits is the same as the one indicated by the high- est_priority_validated[3:0] bits. 3.1.3.3.4 input clock loss of signal there are 4 los input pins (los[3:0 ]) that can be used to disqualify the input clock. if they are set high, then the associated input clock is disqualified to be used as an input clock, and therefore the dplls will not lock to that particular input clock. the 4 los pins can be associated wi th any input clock by setting bits los_en in inn_los_sync_cnfg (1 25 ?2016 integrated device technology, inc. revision 6, july 21, 2016 82p33741 datasheet 3.1.6 apll3 the apll3 is provided for a better jitter and wander performance of the device differential outpu t clocks out10 and out11. apll3 supports 3 clock modes: sonet, ethernet, and ethernet lan. the base frequency for the 3 clock modes are 622.08 mhz, 625 mhz, and 644.53125 mhz respectively. the clock mode selected is determined by the crystal used for the apll. the apll uses a crystal to generat e the respective mode?s base fre- quency. the supported crystal fr equencies are 24.8832 mhz (sonet), 25 mhz (ethernet) and 25.78125 mhz (ethernet lan). the apll sup- ports up to two crystal connections , allowing the apll to support up to two mode?s base frequencies. the input of both apll3 can be derived from one of the dpll1 or dpll2 outputs by configuring inte rnal registers as described in table 12 . the bandwidth for apll3 is set to greater 30 hz (typical), therefore the bandwidth of dpll1 or the dpll2 that is connected to apll3 should be set to 18 hz. 3.1.6.1 external crystals suggestions for crystal options and best matching to apr require- ments, crystal tolerance consi derations and budgets, component place- ment and crystal wiring to achieve minimum capacity are fully detailed in idt an-861, ?recommended crystals and layout guidelines for idt?s vcxo-based synchronization plls. table 13 shows idt (fox) crystals that can be used with apll3. table 12: apll3 input selection crystal apll3 input apll3_mux_cnfg[3:0] apll3_div1_cnfg[7:0 ] apll3_div2_cnfg[26:0] apll3_pd_sel[14:0] apll3_pd_sel[14:0] 24.88320 8100 hz from dpll1 0x04 0x01 0x000012bf 0x0001 0x0c00 24.88320 8100 hz from dpll2 0x0c 0x01 0x000012bf 0x0001 0x0c00 25.00000 8000 hz from dpll1 0x04 0x01 0x000012fb 0x0001 0x0c35 25.00000 8000 hz from dpll2 0x0c 0x01 0x000012fb 0x0001 0x0c35 25.78125 7812.5 hz from dpll1 0x03 0x01 0x0000063f 0x0001 0x0ce4 25.78125 7812.5 hz from dpll2 0x0b 0x01 0x0000063f 0x0001 0x0ce4 table 13: idt(fox) crystals fox part number frequency (mhz) model number 495-24.8832-2 24.88320 fx532b 495-25-141 25.00000 fx532b 495-25.78125-2 25.78125 fx532b 26 ?2016 integrated device technology, inc. revision 6, july 21, 2016 82p33741 datasheet 3.1.7 output clocks & frame sync signals the device supports 11 output cloc ks and 2 frame sync output sig- nals. 3.1.7.1 output clocks out1 can be derived either from dpll1, dpll2, or apll1 selected by out1_mux_cnfg[3:0] out2 ~ out4 can be derived from apll1. out5 ~ out7 can be derived from apll2. out1 to out7 have an output divi der associated with each output. the divider is composed by 2 cascaded dividers, the first divider can be programmed by writing into out n_div1_cnfg[4:0], the second divider can be programmed by writing into outn_div2_cnfg[26:0]. figure 10 shows the diagram for out1 output dividers and relevant register bits. figure 10. out1 output dividers figure 11 shows the diagram for out2 to out7 output dividers and relevant register bits. figure 11. out2 to out7 output dividers out8 and out9 are derived from dpll3, there is an output divider associated with it. a gui (time co mmander) can be used to set the fol- lowing bis in the respective register that are associated with the dpll3 dividers. ? to set the feedback divider, program dpll3_fb_div_cnfg[13:0] bits of dpll3 feedback divider register ? to set the fractional divider, pr ogram dpll3_divn_frac_cnfg[23:0] of dpll3 fractional divider register ? to set the denominator of t he fractional divider, program dpll3_divn_den_cnfg[15:0] bits of dpll3 fractional divider denominator register ? to set the numerator of t he fractional divider, program dpll3_divn_num_cnfg[15:0] bits of dpll3 fractional divider numerator register ? to set the integer divider, program dpll3_int_cnfg[7:0]bits of dpll3 integer divider register out10 and out11 are derived from apll3, refer to table 14 for the output frequency. output ? divider apll1 dpll1 output ? div1 (out1_div1_cnfg[4:0] out1_mux_cnfg[3:0] output ? div2 (out1_div2_cnfg[26:0] dpll2 out1 apll_path phase ? 1 phase ? 2 output ? dividers apll1 apll2 dpll1 output ? div1 (outn_div1_cnfg[4:0] 2< n< 4 ? (from ? apll1) 5< n<7 (from ? apll2) output ? div2 (outn_div2_cnfg[26:0] 2< n< 4 ? (from ? apll1) 5< n<7 (from ? apll2) dpll2 apll_path 2< n< 4 ? (from ? apll1) 5< n<7 (from ? apll2) outn phase ? 1 phase ? 2 27 ?2016 integrated device technology, inc. revision 6, july 21, 2016 82p33741 datasheet out1 to out9 output clocks can be inverted by setting outn_in- vert bit (0: output not inverted, 1: output inverted) in outn_mux- _cnfg register for (1 < n < 7), and in out8_cnfg and out8_cnfg registers for out8 and out9 respectively. the output clocks can be squelched by setting out- n_squelch[1:0] bits (0x: no squelch, 10: squelch to '0', 11: squelch to '1') in outn_mux_cnfg register for (1 < n < 7), and in out8_cnfg and out9_cnfg registers for ou t1 to out9 respectively. out1 to out7 output clocks c an be individually powered down by setting outn_pdn bit to '1' in out n_mux_cnfg register for (1 < n < 7) out10 and out11 can be enabled or disabled by programming out10_enable and out11_enable in the out10 and out11 con- figuration registers respectively. 82p33741 provides a variety of output frequencies from 1hz to 650mhz. apll1 is always enabled and the default frequency for out1, out2, and out3 is respectively 25 mh z, 125 mhz, and 156.25mhz. out4 is squelched by default. by default, out5 to out7 are squel ched. set the proper registers to set desired frequency values for out5 to out7. dpll3 is disabled by default, and if it is enabled, then the default fre- quency for out8 and out9 is respectively 16.384 mhz and 2.048 mhz. apll1, apll2, and the dplls can be configured from an external eeprom after reset. it can be used to set specific start up frequency values as needed by the application. out10 and out11 are powered down by default. apll3 must be configured via the i2c slave interface to set out10 and out11 fre- quency values. 3.1.7.2 frame sync signals either an 8 khz or a 2 khz frame sync, or a 1pps sync signal are output on the frsync_8k_1pps and mfrsync_2k_1pps pins if enabled by the 8k_1pps_en and 2k_1pps en bits respectively. they are cmos outputs. the output sync frequencies are independent of the input sync fre- quency. the output frsync_8k_1pps and mfrsync_2k_1pps fre- quencies are selected through the dpll1 /2_fr_mfr_sync_cnfg registers. any supported clock frequency at the clock input can be associated with the sync signals. the frame sync output signals are derived from the dpll1 and dpll2 output and are aligned with the output clock. they are synchro- nized to the frame sync input signal. the frame/sync output signals align to the first edge of the associ- ated reference clock that occurs after the edge of the frame/sync input signal. the frequency of the associat ed reference clock must be lower or equal to the frequencies of the output clocks that requires to be aligned with the frame/sync pulse signal. if the frame sync input signal with respect to the dpll1/2 selected input clock is above a limit set by the sync_mon_limt[2:0] bits, an external sync alarm will be raised and the frame/sync input signal is dis- abled to synchronize the frame/sync output signals. the external sync alarm is cleared once the frame/sync input signal with respect to the dpll selected input clock is within the limit. if it is within the limit, whether frame/sync input signal is enabled to synchronize the frame sync output signal is determined by the auto_ext_sync_en bit and the ext_sync_en bit. when the frame/sync input signal is enabled to synchronize the frame/sync output signal, it is adjus ted to align itself with the dpll selected input clock. table 14: outputs on out10~11 outn_odsel0/1[2:0] (output divider) outputs on out10~11 1 sonet (xtaln = 24.8832 mhz) ethernet (xtaln = 25 mhz) ethernet * 66/64 (xtaln = 25.78125 mhz) 1 622.08 mhz 625 mhz 644.53125 mhz 2 311.04 mhz 312.5 mhz 322.265625 mhz 4 155.52 mhz 156.25 mhz 161.1328125 mhz 5 125 mhz 8 2 77.76 mhz 25 3 25 mhz (outn_enable = 0) output ?n? is disabled (outn_enable = 1) output ?n? is enabled note: 1. the blank cell means the configuration is reserved. the proper xtal must be populated for xtal1~2 based on the selected mode. 2. out11 only 3. out10 only 28 ?2016 integrated device technology, inc. revision 6, july 21, 2016 82p33741 datasheet by default, the falling edge of the fr ame/sync input signal is aligned with the rising edge of the dpll1/2 selected input clock. the rising edge of frame/sync input signal can be set to be aligned with the rising edge of the dpll1/2 selected input clock by setting sync_edge bit to ?1? in dpll1/2_sync_edge_cnfg register. the ex_sync_alarm_mon bit i ndicates whether frame/sync input signal is in external sync al arm status. the external sync alarm is indicated by the ex_sync_alarm bit. if the ex_sync_alarm bit is ?1?, the occurrence of the external sync alarm will trigger an interrupt. the 8 khz frame pulse, the 2 kh z frame pulse, and the 1pps sync signal can be inverted by setting the 8k_1pps_inv and 2k_1pps_inv bits of frame sync and multiframe sync output configuration register. the 8 khz and the 2 khz frame sync outputs can be 50:50 duty cycle or pulsed, as determined by the 8k_p ul and 2k_pul bits respectively. when they are pulsed, the pulse wi dth derived from dpll1 is defined by the period of out1, and the pulse wi dth derived from dpll2 is defined by the period of an internal clock. they are pulsed on the position of the falling or rising edge of the standard 50:50 duty cycle, as selected by the 2k_8k_pul_position bit of frame sync and multiframe sync output configuration register. 3.1.8 input and output phase control the device has several features to allow a tight control of the phase on the input and output clocks. 3.1.8.1 dpll1 and dpll2 phase offset control the phase offset of the dpll1/2 selected input clock with respect to the dpll1/2 output can be adjusted. if the device is configured as the active pll in a redundancy system, then the ph_offset_en bit deter- mines whether the input-to-output pha se offset is enabled. if the device is configured as the inactive pll in a redundancy system, then the input-to-output phase offset is al ways enabled. if enabled, the input-to- output phase offset can be adjusted by setting the ph_off- set_cnfg[28:0] bits in dpll1/2 phas e offset configuration register. the register value is a 2's complem ent phase offset with a resolution of 0.0745ps and a total range of [20us, - 20us]. the input-to-output phase offset can be calculated as follows: phase offset (ps) = ph_offset[28:0] x 0.0745 3.1.8.2 input phase control all the inputs phase can be controll ed individually. they can be pro- grammed with a resolution of 0.61 ns and a range of [77.5 ns,-78.1ns] by setting inn_phase_offset_cnfg[7:0] bits (1 < n < 12) in the input phase offset configuration register. t he register value is a 2's comple- ment phase offset, the default is ze ro. the programmed offset is auto- matically applied to the dpll1 and dpll2 when a particular input is selected. if the manual dpll1 and dpll2 phase offset control is used then the per-input phase offset is not applied. 3.1.8.3 output phase control the output phase can be controlled individually for outputs out1 to out7. there is the coarse phase control that allows the output phase to be adjusted as low as 1.6ns. th ere is a fine phase adjustment that allows the output phase to be adjusted as low as 187.27 ps. the total range is +/-180 o . there are two registers associat ed with the coarse phase adjust- ment, the outn_ph1_cnfg (1 < n < 7) and the outn_ph2_cnfg (1 < n < 7) registers. the outn_ph1_ cnfg register is associated with output divider 1 as shown in figure 10 and figure 11 , the phase can be adjusted by a step size that is equal to the period of the input of clock of the output div1, the number set in the outn_ph1_cnfg register should not be larger than the number set in outn_div1_cnfg register. the outn_ph2_cnfg register is associated with output divider 2 as shown in figure 10 and figure 11 , the phase can be adjusted by a step size that is equal to the period of the input of clock of the output div2, the number set in the outn_ph2_cnfg r egister should not be larger than the number set in outn_div2_cnfg register. there is a register that is asso ciated with the fine phase adjustment, the outn_fine_cnfg (1 < n < 7). for the fine phase adjustment, the output clocks must be output from the aplls, the phase can be adjusted by a step size that is equal to the 1/2 of the period of the vco. for ethernet clocks the vco frequenc y is 2.5ghz, for ethernet lan phy the vco frequency is 2.578125 ghz, and for sonet/sdh clocks the vco frequency is 2.48832 ghz. out1 can be output from the dplls, and in that case the fine phase adjustment is not available, it is only available if the clocks are output from the aplls. the output phase adjustments are not available for out8, out9, out10, and out11. 29 ?2016 integrated device technology, inc. revision 6, july 21, 2016 82p33741 datasheet 4 power supply filtering techniques to achieve optimum jitter perform ance, power supply filtering is required to minimize s upply noise modulation of the output clocks. the common sources of power supply noi se are switch power supplies and the high switching noise from the outputs to the internal pll. the 82p33741 provides separate vdda and vddao power pins for the internal analog pll, it also prov ides vddd and vdddo pins for the core logic as well as i/o driver circuits. the suggested power decoupling scheme is shown in figure 12 . 30 ?2016 integrated device technology, inc. revision 6, july 21, 2016 82p33741 datasheet figure 12. 82p33741 power decoupling scheme vddd d5, ? f7 vssd d4, ? f6 vcc3v3 vdddo e4, ? e6, ? l7, ? m8 vssdo f4, ? e7, ? k7, ? m7 vcc3v3 vdda c1, ? d2, ? k1, ? k2 vssa one ? 0.1uf ? per ? pin vcc3v3 cap1,2 100nf c9, ? a9 vssa b9 10uf vddao a5, ? a7, ? b2, ? b3, ? l4, ? m4 vssao b5, ? b7, ? b1, ? b4, ? k4, ? m3 one ? 0.1uf ? per ? pin one ? 0.1uf ? per ? pin vddd_1p8 0.1uf h12, ? l10 vssd h11, ? l9 one ? 0.1uf ? per ? pin 10uf vcc1v8 0.1uf cap3 d8 vssa e8 0.1uf one ? 0.1uf ? per ? pin vcc3v3 0.1uf 10uf 0.1uf 0.1uf 0.1uf 10uf 0.1uf 0.1uf 0.1uf 10uf 0.1uf 0.1uf d1, ? c2, ? l1, ? l2 0.1uf 10uf 0.1uf 0.1uf 10uf vdda c6, ? c7, ? f2 ? , ? f9 , ? g2, ? h2 vssa one ? 0.1uf ? per ? pin vcc3v3 0.1uf 10uf 0.1uf 0.1uf d6, ? d7, ? e2, ? f3, ? f8 , ? h3 31 ?2016 integrated device technology, inc. revision 6, july 21, 2016 82p33741 datasheet 5 microprocess or interface the microprocessor interface provi des access to read and write the registers in the device. the micr oprocessor interface supports i2c. 5.1 i2c slave mode 5.1.1 i2c device address the default value for the higher 4- bit address is 4?b1010, the 2-bit address is set by pins i2c_ad2, i2c_ad1, and the lower bit address i2c_ad0 is used to address the c onfiguration of dplls/apll1/2 and apll3. 5.1.2 i2c bus timing figure 13 shows the definition of i2c bus timing. figure 13. definiti on of i2c bus timing sda scl t low t f t hd: sta t hd: dat t high t su: dat t f t su: sta t hd: sta t sp t su: sto t buf s sr ps t r t r 32 ?2016 integrated device technology, inc. revision 6, july 21, 2016 82p33741 datasheet table 15: timing definition for standard mode and fast mode (1) symbol parameter standard mode fast mode unit min max min max scl serial clock frequency 0 100 0 400 khz t hd; sta hold time (repeated) start condition. after this period, the first clock pulse is generated 4.0 - 0.5 - ? s t low low period of the scl clock 4.7 - 1.3 - ? s t high high period of the scl clock 4.0 - 0.6 - ? s t su; sta set-up time for a repeated start condition 4.7 - 0.6 - ? s t hd; dat data hold time: for cbus compatible masters for i 2 c-bus devices 5.0 0 (2) - 3.45 (3) - 0 (2) - 0.9 (3) ? s t su; dat data set-up time 250 - 100 (4) -ns t r rise time of both sda and scl signals - 1000 20 + 0.1cb (5) 300 ns t f fall time of both sda and scl signals - 300 20 + 0.1cb (5) 300 ns t su; sto set-up time for stop condition 4.0 - 0.6 - ? s t buf bus free time between a stop and start condition 4.7 - 1.3 - ? s c b capacitive load for each bus line - 400 - 400 pf v nl noise margin at the low level for each connected device (including hysteresis) 0.1vdd - 0.1vdd - v v nh noise margin at the high level for each connected device (including hysteresis) 0.2vdd - 0.2vdd - v t sp pulse width of spikes which must be suppressed by the input filter 050050ns note: 1. all values referred to v ihmin and v ilmax levels (see table 23 ) 2. a device must internally provide a hold time of at least 300 ns for the sda signal (referred to the v ihmin o f the scl signal) to bridge the undefined region of the fall- ing edge of scl. 3. the maximum t hd; dat h as only to be met if the device does not stretch the low period (t low ) of the scl signal. 4. a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system, but the requirement t su; dat 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the s cl signal, it must output the next data bit to the sda line t rmax + t su; dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c-bus specification) before the scl line is released. 5. c b = total capacitance of one bus line in pf. if mixed with hs-mode device, faster fall-times according to table 24 allowed. n/a = not applicable 33 ?2016 integrated device technology, inc. revision 6, july 21, 2016 82p33741 datasheet 5.1.3 supported transactions the supported types of trans actions are shown below. figure 14. i2c slave interface supported transactions the registers are divided up into pages of 128 bytes with each byte having a separate address. multi-by te registers need to be accessed in multiple read/write cycles. addres s 0x7f is reserved for the page index pointer. all register accesses are done as 8 bit i2c cycles. the 8-bit address refers to the register offset within the active page. if access to a different page is needed then a separate i2c write must be performed to the page register (0x7f). this makes the new page active and then 8 bit reads and writes can be perform ed anywhere within that page. note that accesses to multi-byte registers should not be interrupted by accesses to other addresses, because that may cause the data to be corrupted. the access of the multi-byte registers is different from the sin- gle-byte registers. take the dpll1 priority table registers (00h and 01h in page 2) as an example, the write op eration for the multi-byte registers follows a fixed sequence. the register (00h) is configured first and the register (01h) is configured last. t he two registers are configured contin- uously and should not be interrupted by any operation. the dpll1 prior- ity table configuration will take e ffect after all the two registers are configured. during read operation, the register (00h) is read first and the register (01h) is read last. the priori ty table configuration register read- ing should be continuous and not be interrupted by any operation. 5.2 i2c master mode the 82p33741 has the capability to read from an external i2c eeprom upon exit from reset. this reduces the start-up load on the microprocessor by programming the registers in the device-address space 101_0xx1 (registers in device- address space 101_0xx0 must still be written by the microprocessor) . this mode uses the mpu_mode1/ i2cm_scl and the mpu_mode0/i2cm_sda pins as the serial clock and the serial data respectively, it requires that both these pins be pulled high through resistors (these resi stor values are dependent on the bus capacitance and i2c speed of the appl ication). access to the 82p33741 registers through the microprocessor interface i2c serial port is not available until the eeprom reading process is completed. as an i 2 c bus master, the 82p33741 will support the following: ? 8 kbit (1023 x 8) i2c eeprom with device address 1010000 (for the base block) ? sequential read (block read) of t he entire memory-map for device- excluding apll3, from byte-address 0x000 to 0x39e ? 7-bit device address mode ? validation of the eeprom read data via ccitt-8 crc check against value stored in memory-map address 0x39e ? support for 100khz and 400khz operation with speed programma- bility. if bit 7 is set at memory-map address 0x001, the 82p33741 will shift from 100khz operation to 400khz operation. ? 2-byte word-addressing (1-byte word addressing is supported by offsetting the memory-map upwards 1 address in the eeprom) ? read will abort with an alarm (rd_eeprom_err interrupt status set) if any of the following condi tions occur: slave nack, crc fail- ure, slave response time-out table 16: description of i2c sl ave interface supported transactions operation description current read reads a burst of data from an internal determined starting addres s, this starting address is equal to the last address accessed during the last read or write operation, incremented by one. if the address exceeds the address space, it will start from 0 aga in. sequential read reads a burst of data from a specified address space. the starting address of the space is specified as offset a ddress. sequential write writes a burst of data to a specified address space, the starting address of the space is specified as offset address. current read s dev addr + r a data 0 a data 1 a a data n a p sequential read s dev addr + w a data 0 a data 1 a a data n a p s r dev addr + r a sequential write s dev addr + w a data 0 p a data 1 a a data n a from master to slave from slave to master s = start s r = repeated start a = acknowledge a = not acknowledge p=stop offset addr a offset addr a 34 ?2016 integrated device technology, inc. revision 6, july 21, 2016 82p33741 datasheet as the 82p33741 i2c master bus is meant only to read from a single eeprom, it has the following restrictions: ? no support for multi-master ? no support for slave clock stretching ? no support for i2c start byte protocol ? no support for eeprom chaining ? no support for writing to external i2c devices including the eeprom used for booting 5.2.1 i2c boot-up initialization mode eeprom mode is enabled via setting the mpu_mode[1:0] pins high (through two separate pull-up resistors). once the rstb input has been asserted (low) and then de-asserted (high) and the device internal calibration has been completed, the 82p33741 will perform a short block read at 100 khz to program the eeprom read speed (100 khz or 400 khz). the 82p33741 will then perform a block read to program all the device configuration registers, and check the crc of the eeprom data. during the boot-up eeprom-reading process, the 82p33741 will not respond to microprocessor serial control port accesses. once the initialization process is completed, the contents of any of the device con- figuration registers can be further altered by the microprocessor, if desired. the 82p33741 can work with eepr oms supporting 2-byte word- addresses or 1-byte word-addresses by using 2-byte word addressing for both. this works in the us ual manner for eeproms supporting 2- byte word addresses, and gives an address-to-address match between eeprom and memory-map. for eeproms supporting only 1-byte word addresses, the second address byte will cause an addition incre- ment of the address counter, and the memory-map will be read at the next highest eeprom address,.i.e memory-map (csr) address 0x00 will be read from eeprom address 0x01, and memory map address 0x39e will be read from eeprom address 0x39f. if a nack is received to any of the read cycles performed by the 82p33741 during the initialization proces s, or if the crc does not match the one stored in memory-map addres s 0x39e, the boot process will be restarted. this restart can happen up to three times before an abort is declared and the rd_eeprom_err interr upt status bit is set. also on rd_eeprom_err the mpu_mode1/ i2cm_scl and mpu_mode0/ i2cm_sda pins are both held low until the interrupt status bit is cleared or the device is reset. the sugges ted method for dealing with rd_ee- prom_err is to externally set the mpu_mode[1:0] pins to 00 and then reset the 82p33741 so that it will boot into i2c serial port mode. after a successful eeprom boot, the 82p33741 will stop toggling the mpu_mode1/ i2cm_scl and mpu_mode0/i2cm_sda pins, returning them to static high va lues, and the rd_eeprom_done inter- rupt status bit will be set. the i2c serial port will now respond to micro- processor reads and writes to t he appropriate i2c device address. 5.2.2 eeprom memory map notes the eeprom memory-map is the same as the control and status register (csr) map with the fo llowing additions and constraints: 1. for eeproms supporting 2-byte word-address, the memory-map addresses are the same as the epprom addresses; for eeproms supporting 1-byte word-address, the memory-map addresses will by mapped to the next address in the eeprom, i.e. memory-map address 0x00 will be read from eeprom address 0x01, and memory-map address 0x39e will be read from eeprom address 0x39f. 2. memory-map address 0x001, bit 7 is the eeprom read speed (0 for 100 kps, 1 for 400 kbps) 3. memory-map address 0x39e is the crc-8 of the memory-map from 0x000 to 0x39d (the standard cc itt crc-8 with the data width and result width being 8; the polynomial is (0, 1, 2, 8) or "0x07"). nb: all memory-map addresses from 0x000 to 0x39d are included in the sequential calculation of crc, including those not used in the csr - it is recommend that data at unused addresses be set to 0x00. 4. memory-map addresses 0x392 to 0x39d must be set to the default values shown in the csr documentation. 5. the device address at memo ry-map address 0x00f must match the address set by the board. 6. each memory-map address that is a multiple of 0x7f must contain the pointer to the next page of the csr i.e 0x07f 0x01 0x0ff 0x02 0x17f 0x03 0x1ff 0x04 0x27f 0x05 0x2ff 0x06 0x37f 0x07 35 ?2016 integrated device technology, inc. revision 6, july 21, 2016 82p33741 datasheet 6jtag this device is compliant with the ieee 1149.1 boundary scan stan- dard except the following: ? the output boundary scan cells do not capture data from the core and the device does not support extest instruction; the jtag interface timing diagram is shown in figure - 15 . figure 15. jtag interface timing diagram table 17: jtag timing characteristics symbol parameter min typ max unit t tck tck period 100 ns t s tms / tdi to tck setup time 25 ns t h tck to tms / tdi hold time 25 ns t d tck to tdo delay time 50 ns tck tdo tms tdi t tck t s t h t d 36 ?2016 integrated device technology, inc. revision 6, july 21, 2016 82p33741 datasheet 7 thermal management the device operates over the industry temperature range -40c ~ +85c. to ensure the functionality and re liability of the device, the maxi- mum junction temperature t jmax should not exceed 125c. in some applications, the device will consume more power and a thermal solution should be provided to ensure the junction temperature t j does not exceed the t jmax . 7.1 junction temperature junction temperature t j is the temperature of package typically at the geographical center of the chip where t he device's electric al circuits are. it can be calculated as follows: equation 1: t j = t a + p x ? ja where: ? ja = junction-to-ambient thermal resistance of the package t j = junction temperature t a = ambient temperature p = device power consumption in order to calculate juncti on temperature, an appropriate ? ja must be used. the ? ja is shown in table 18 : table 18 has the thermal results based on jedec standard condi- tions. it is industry practice and idt pr actice to publish these results. if the pcb design differs from t he jedec standard conditions, then the thermal results will be different. 7.2 thermal release path in order to maximize both the removal of heat from the package, electrical grounding from the package to the board can be done through thermal vias to effectively conduct fr om the surface of the pcb to the ground plane(s). the vias act as ?heat pipes?. the number of vias (i.e. ?heat pipes?) are application s pecific and dependent upon the package power dissipation as well as electric al conductivity requirements. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. it is recommended to use as many vias connected to ground as po ssible. it is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz cop- per via barrel plating. these re commendations are to be used as a guideline only. table 18: thermal data parameter symbol conditions pk g typ values (c/w) notes thermal resistance ? jc junction to case bag144 6.8 jedec pcb (8x8 matrix) ? jb junction to base 16.2 ? ja1 junction to air, still air 34.8 ? ja2 junction to air, 1 m/s air flow 28.8 ? ja3 junction to air, 2 m/s air flow 26.7 ? ja4 junction to air, 3 m/s air flow 25.7 37 ?2016 integrated device technology, inc. revision 6, july 21, 2016 82p33741 datasheet 8 electrical specifications 8.1 absolute maximum rating 8.2 recommended oper ation conditions table 19: absolute maximum rating symbol parameter min max unit v dda , v ddao , v dddo ,v ddd supply voltage v dda , v ddao , v dddo ,v ddd -0.5 3.6 v v ddd_1_8 supply voltage v ddd_1_8 -0.5 1.98 v v incmos input voltage (cmos and open drain pins) -0.5 5.5 v v indiff input voltage (differential pins) -0.5 v ddd + 0.5 v v inan input voltage (analog pins) -0.5 2.2 v i outcont output current (continuous current) 50 ma i outsurge output current (surge current) 100 ma t a ambient operating temperature range -40 85 c t stor storage temperature -50 150 c note: cdm classification - class iii (jesd22 - c101) hbm classification - class 2 (js-001-2010) table 20: recommended operation conditions symbol parameter min typ max unit test condition v dda , v ddao , v dddo ,v ddd power supply (dc voltage) 3.135 3.3 3.465 v v ddd_1_8 power supply (dc voltage) v ddd_1_8 1.71 1.8 1.89 v t a ambient temperature range -40 85 c i dda analog supply current 480.8 548.48 ma i ddd digital supply current (v ddd ) 41.90 62.05 ma i ddd_1_8 digital supply current (v ddd_1_8 ) 81.09 89.49 ma i dddo digital output supply current 45.18 64.77 ma all outputs enabled i ddao analog output supply current 168.46 220.96 ma all outputs enabled, unloaded analog output supply current (loaded) 248.26 308.74 ma all outputs enabled, 6 lvpecl outputs loaded with 150 ohms to gnd p tot total power dissipation 2.58 3.29 w all outputs enabled, excluding the loading 38 ?2016 integrated device technology, inc. revision 6, july 21, 2016 82p33741 datasheet 8.3 i/o specifications 8.3.1 cmos input / output port table 21: cmos input port electrical characteristics parameter description min typ max unit test condition v ih input voltage high 2 v v il input voltage low 0.8 v i in input current 10 ? a table 22: cmos input port with internal pull-up resistor elect rical characteristics parameter description min typ max unit test condition v ih input voltage high 2 v v il input voltage low 0.8 v p u pull-up resistor 50 k ? except rstb pin p u pull-up resistor (rstb pin) 25 k ? i in input current 150 ? a table 23: cmos input port with internal pull-down resistor el ectrical characteristics parameter description min typ max unit test condition v ih input voltage high 2 v v il input voltage low 0.8 v p d pull-down resistor 50 k ? i in input current 150 ? a table 24: cmos output port electrical characteristics application pin parameter description min typ max unit test condition output clock v oh output voltage high 2.4 vdd v i oh = -4 ma v ol output voltage low 0.4 v i ol = 4 ma t r rise time 2.2 ns c load = 15 pf t f fall time 2.2 ns c load = 15 pf other output v oh output voltage high 2.4 v i oh = -2 ma v ol output voltage low 0.4 v i ol = 2 ma t r rise time 7 20 ns c load = 50 pf t f fall time 7 20 ns c load = 50 pf 39 ?2016 integrated device technology, inc. revision 6, july 21, 2016 82p33741 datasheet 8.3.2 lvpecl / lvds input / output port 8.3.2.1 pecl input port figure 16. recommended pecl input port line termination in_pos in_neg 1 pps to 650 mhz 50 (transmission line) v dd (+ 3.3 v) 130 82 gnd v dd (+ 3.3 v) 130 82 gnd 50 (transmission line) ? ? ? ? ? ? table 25: lvpecl input port electrical characteristics parameter description min typ max unit test condition v il input low voltage, differential inputs vdd - 2.5 vdd - 1.5 vdd - 0.5 v v ih input high voltage, differential inputs vdd - 2.4 vdd - 1.4 vdd - 0.4 v v id input differential voltage 0.1 0.7 1.4 v v il_s input low voltage, single-ended input vss vdd - 1.95 vdd - 1.5 v v ih_s input high voltage, single-ended input vdd - 1.3 vdd - 0.9 vdd v i ih input high current, input differential voltage v id = 1.4 v 10 ? a i il input low current, input differential voltage v id = 1.4 v -10 ? a note: 1. assuming a differential input voltage of at least 100 mv. 2. unused differential input terminated to vdd-1.4 v. 40 ?2016 integrated device technology, inc. revision 6, july 21, 2016 82p33741 datasheet 8.3.2.2 lvpecl output port 8.3.2.2.1 lvpecl termination for 3.3 v the clock layout topology shown bel ow is a typical termination for lvpecl outputs. the two different layouts mentioned are recom- mended only as guidelines. the differential outputs are low impedance follower outputs that gen- erate ecl/lvpecl compatible outputs. therefore, terminating resistors (dc current path to ground) or current sources must be used for func- tionality. these outputs are designed to drive 50 ? transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. figure 17 and figure 18 show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. figure 17. 3.3v lvpecl output termination figure 18. 3.3v lvpecl output termination 8.3.2.2.2 lvpecl termination for 2.5 v figure 19 and figure 20 show examples of termination for 2.5v lvpecl driver. these terminations are equivalent to terminating 50 ? to vcco ? 2v. for vcco = 2.5v, the vcco ? 2v is very close to ground level. the r3 in figure 20 can be eliminated and the termination is shown in figure 21 . figure 19. 2.5v lvpecl output termination figure 20. 2.5v lvpecl output termination figure 21. 2.5v lvpecl output termination r1 84 r2 84 3.3v r3 125 r4 125 z o = 50 z o = 50 lvpecl input 3.3v 3.3v + _ 3.3v v cc - 2v r1 50 r2 50 rtt z o = 50 z o = 50 + _ rtt = * z o 1 ((v oh + v ol ) / (v cc C 2)) C 2 3.3v lvpecl input 41 ?2016 integrated device technology, inc. revision 6, july 21, 2016 82p33741 datasheet 8.3.3 lvds input / output port 8.3.3.1 lvds input port figure 22. recommended lvds input port line termination table 26: lvpecl output port electrical characteristics parameter description min typ max unit test condition v oh output high voltage; note 1 v cco ? 1.3 v cco ? 0.7 v v ol output low voltage; note 1 v cco ? 2.0 v cco ? 1.5 v v swing peak-to-peak output voltage swing 0.6 1.0 v t rise/ t fall output rise/fall time 80 400 ps 20% to 80% note 1: outputs te rminated with 50 ? to v cco ? 2v in_pos in_neg 50 (transmission line) 100 1 pps to 650 mhz 50 (transmission line) ? ? ? table 27: lvds input port electrical characteristics parameter description min typ max unit test condition v cm input common-mode voltage range 200 1200 2200 mv v diff input peak differential voltage 100 350 900 mv v idth input differential threshold -100 100 mv r term external differential termination impedance 100 ? 42 ?2016 integrated device technology, inc. revision 6, july 21, 2016 82p33741 datasheet 8.3.3.2 lvds output port lvds driver termination for a general lvds interface, the recommended value for the termi- nation impedance (zt) is between 90 ? and 132 ? . the actual value should be selected to match the differential impedance (z0) of your transmission line. a typical point-t o-point lvds design uses a 100 ? par- allel resistor at the receiver and a 100 ? differential transmission-line environment. in order to avoid any transmission-line re flection issues, the components should be surface mounted and must be placed as close to the receiver as possible. id t offers a full line of lvds compliant devices with two types of output st ructures: current source and voltage source. the standard termination schem atic as shown at the top part of figure 23 can be used with either type of output structure. the termina- tion schematic shown at the bottom part of figure 23 , which can also be used with both output types, is an optional termination with center tap capacitance to help filter common mode noise. the capacitor value should be approximately 50pf. if using a non-standard termination, it is recommended to contact idt and confirm if the output structure is cur- rent source or voltage source type. in addition, since these outputs are lvds compatible, the input rece iver?s amplitude and common-mode input range should be verified for compatibility with the output. figure 23. recommended lvds output port line termination table 28: lvds output port electrical characteristics parameter description min typ max unit test condition v od differential output voltage 247 454 mv ? v od v od magnitude change 50 mv v os offset voltage 1.125 1.375 v ? v os v os magnitude change 50 mv t rise/ t fall output rise/fall time 90 400 ps 20% to 80% 43 ?2016 integrated device technology, inc. revision 6, july 21, 2016 82p33741 datasheet 8.3.4 output clock duty cycle table 29: output clock duty cycle (out1 - out9) clock output frequency min typ max unit test condition f out <570mhz 45 55 % f out > 570mhz 35 65 % note: output duty cycle configured using apll1 or apll2. table 30: output clock duty cycle (out10 - out11) clock output frequency min typ max unit test condition f out <600mhz 47 53 % f out > 600mhz 45 55 % 44 ?2016 integrated device technology, inc. revision 6, july 21, 2016 82p33741 datasheet 8.3.5 wiring the differential input to accept single-ended levels figure 24 shows how a differential input can be wired to accept single ended levels. the reference voltage v ref = v cc /2 is gener- ated by the bias resistors r1 and r2. the bypass capacitor (c1) is used to help filter noise on t he dc bias. this bias circuit should be located as close to the input pin as possible. the ratio of r1 and r2 might need to be adjusted to position the v ref in the center of the input voltage swing. for example, if the input clock swing is 2.5v and v cc = 3.3v, r1 and r2 value should be adjusted to set v ref at 1.25v. the values below are for when both the single ended swing and v cc are at the same voltage. this configuration requires that the su m of the output impedance of the driver (ro) and the series resi stance (rs) equals the transmission line impedance. in addition, matched termination at the input will attenuate the signal in half. this can be done in one of two ways. first, r3 and r4 in parallel should equal the transmission line impedance. for most 50 ? applications, r3 and r4 can be 100 ? . the values of the resistors can be increased to reduce the loading for slower and weaker lvcmos driver. when using single-ended signaling, the noise rejection ben efits of differential signaling are reduced. even though the differential input can handle full rail lvcmos signaling, it is recommended that the amplitude be reduced. the datasheet specifie s a lower differential amplitude, however this only applies to differential signals. for single-ended applications, the swing can be larger, however v il cannot be less than -0.3v and v ih cannot be more than v cc + 0.3v. suggest edge rate faster than 1v/ns. though some of the recommended components might not be used, the pads should be placed in the layout. they can be utilized for debugging purposes. the data- sheet specifications are characterized and guaranteed by using a differential signal. figure 24. recommended schematic for wiring a differential input to accept single-ended levels vth = vcc*[r2/(r1+r2)] for the example in figure 24 , r1 = r2, so vth = vcc/2 =1.65 v the suggested single-ended signal input: v ihmax = vcc v ilmin = 0 v v swing = 0.6 v ~ vcc dc offset (swing center) = vth/2 +/- v swing *10% 45 ?2016 integrated device technology, inc. revision 6, july 21, 2016 82p33741 datasheet 8.4 jitter performance table 31: gigabit ethernet ou tput clock jitter generation (jitter measured on one differential output of apll3 with all other outputs disabled) output frequency rms jitter typ (ps) rm s jitter max (ps) test filter notes 25 mhz 0.26 0.32 2.5 khz - 5 mhz itu-t g.8262 limit 0.5 ui p-p (1 ui = 0.8 ns) 0.26 0.31 10 khz - 5 mhz idt target test filter for 10gbe 0.19 0.24 637 khz - 5 mhz ieee 802.3-2008 limit 0.24 ui p-p / 0.0174 ui rms (1 ui = 0.8 ns) 0.20 0.23 10 khz - 1 mhz 125mhz 0.24 0.30 2.5 khz to 10 mhz itu-t g.8262 limit 0.5 ui p-p (1 ui = 0.8 ns) 0.25 0.31 10 khz - 20 mhz idt target test filter for 10gbe 0.15 0.19 637 khz - 10 mhz ieee 802.3-2008 limit 0.24 ui p-p / 0.0174 ui rms (1 ui = 0.8 ns) 0.22 0.39 1 khz - 1 mhz 0.20 0.23 10 khz - 1 mhz 156.25mhz 0.24 0.29 10 khz - 20 mhz idt target test filter for 10gbe 0.25 0.30 20 khz - 40 mhz itu-t g.8262 limit 0.5 ui p-p (1 ui = 100.47 ps) 0.14 0.19 1 mhz - 30 mhz 0.10 0.12 1.875 mhz - 20 mhz ieee 802.3-2008 limit 0.28 ui p-p / 0.0203 ui rms (1 ui = 100.47 ps) 0.22 0.39 1 khz - 1 mhz 0.20 0.23 10 khz - 1 mhz 46 ?2016 integrated device technology, inc. revision 6, july 21, 2016 82p33741 datasheet 625mhz 0.23 0.28 10 khz - 20 mhz idt target test filter for 10gbe 0.25 0.31 20 khz - 80 mhz itu-t g.8262 limit 0.5 ui p-p (1 ui = 100.47 ps) itu-t g.8262 limit 1.2 ui p-p (1 ui = 38.79 ps) 0.12 0.16 1 mhz - 30 mhz 0.07 0.09 1.875 mhz - 20 mhz ieee 802.3-2008 limit 0.28 ui p-p / 0.0203 ui rms (1 ui = 100.47 ps) 0.22 0.38 1 khz - 1 mhz 0.21 0.24 10 khz - 1 mhz note 1: dpll locked to input clock note 2: for ber = 10?12, rms jitter = p-p jitter/13.8 per ieee 802.3-2008 and ieee 802.3ae-2002 section 48b.3.1.3.1 table 31: gigabit ethernet ou tput clock jitter generation (jitter measured on one differential output of apll3 with all other outputs disabled) output frequency rms jitter typ (ps) rm s jitter max (ps) test filter notes table 32: gigabit ethernet ou tput clock jitter generation (jitter measured on one differential output of apll1/2 with one differential output enabled) output frequency rms jitter typ (ps) rm s jitter max (ps) test filter notes 25 mhz 0.71 1.31 2.5 khz - 5 mhz itu-t g.8262 limit 0.5 ui p-p (1 ui = 0.8 ns) 0.57 0.84 12 khz - 5 mhz 0.28 0.42 637 khz - 5 mhz ieee 802.3-2008 limit 0.24 ui p-p / 0.0174 ui rms (1 ui = 0.8 ns) 125mhz 0.72 1.40 2.5 khz to 10 mhz itu-t g.8262 limit 0.5 ui p-p (1 ui = 0.8 ns) 0.58 0.86 12 khz - 20 mhz 0.20 0.29 637 khz - 10 mhz ieee 802.3-2008 limit 0.24 ui p-p / 0.0174 ui rms (1 ui = 0.8 ns) 47 ?2016 integrated device technology, inc. revision 6, july 21, 2016 82p33741 datasheet 156.25mhz 0.56 0.85 12 khz - 20 mhz 0.52 0.99 20 khz - 40 mhz itu-t g.8262 limit 0.5 ui p-p (1 ui = 100.47 ps) 0.23 0.30 1 mhz - 30 mhz 0.16 0.22 1.875 mhz - 20 mhz ieee 802.3-2008 limit 0.28 ui p-p / 0.0203 ui rms (1 ui = 100.47 ps) note 1: dpll locked to input clock note 2: for ber = 10?12, rms jitter = p-p jitter/13.8 per ieee 802.3-2008 and ieee 802.3ae-2002 section 48b.3.1.3.1 table 32: gigabit ethernet ou tput clock jitter generation (jitter measured on one differential output of apll1/2 with one differential output enabled) output frequency rms jitter typ (ps) rm s jitter max (ps) test filter notes table 33: gigabit ethernet ou tput clock jitter generation (jitter measured on one cmos output of apll1/2 with one cmos output enabled) output frequency rms jitter typ (ps) rm s jitter max (ps) test filter notes 25 mhz 0.71 1.26 2.5 khz - 5 mhz itu-t g.8262 limit 0.5 ui p-p (1 ui = 0.8 ns) 0.55 0.83 12 khz - 5 mhz 0.23 0.30 637 khz - 5 mhz ieee 802.3-2008 limit 0.24 ui p-p / 0.0174 ui rms (1 ui = 0.8 ns) 125mhz 0.78 2.32 2.5 khz to 10 mhz itu-t g.8262 limit 0.5 ui p-p (1 ui = 0.8 ns) 0.62 0.94 12 khz - 20 mhz 0.21 0.31 637 khz - 10 mhz ieee 802.3-2008 limit 0.24 ui p-p / 0.0174 ui rms (1 ui = 0.8 ns) note 1: dpll locked to input clock note 2: for ber = 10?12, rms jitter = p-p jitter/13.8 per ieee 802.3-2008 and ieee 802.3ae-2002 section 48b.3.1.3.1 48 ?2016 integrated device technology, inc. revision 6, july 21, 2016 82p33741 datasheet table 34: gigabit ethernet lan output clock jitter generation (jitter measured on one differential output of apll3 with all other outputs disabled) output frequency rms jitter typ (ps) rm s jitter max (ps) test filter notes 161.1328125 mhz 0.23 0.27 10 khz - 20 mhz idt target test filter for 10gbe 0.25 0.29 20 khz - 40 mhz itu-t g.8262 limit 0.5 ui p-p (1 ui = 96.97 ps) 0.14 0.19 1 mhz - 30 mhz 0.09 0.12 1.875 mhz - 20 mhz ieee 802.3-2008 limit 0.28 ui p-p / 0.0203 ui rms (1 ui = 96.97 ps) 0.20 0.22 10 khz - 1 mhz 322.265625 mhz 0.23 0.26 10 khz - 20 mhz idt target test filter for 10gbe 0.25 0.30 20 khz - 80 mhz itu-t g.8262 limit 0.5 ui p-p (1 ui = 96.97 ps) 0.13 0.16 1 mhz - 30 mhz 0.07 0.10 1.875 mhz - 20 mhz ieee 802.3-2008 limit 0.28 ui p-p / 0.0203 ui rms (1 ui = 96.97 ps) 0.20 0.22 10 khz - 1 mhz 644.53125 mhz 0.23 0.27 10 khz - 20 mhz idt target test filter for 10gbe 0.24 0.28 20 khz - 80 mhz itu-t g.8262 limit 0.5 ui p-p (1 ui = 96.97 ps) 0.12 0.15 1 mhz - 30 mhz 0.07 0.09 1.875 mhz - 20 mhz ieee 802.3-2008 limit 0.28 ui p-p / 0.0203 ui rms (1 ui = 96.97 ps) 0.20 0.23 10 khz - 1 mhz note 1: dpll locked to input clock note 2: for ber = 10?12, rms jitter = p-p jitter/13.8 per ieee 802.3-2008 and ieee 802.3ae-2002 section 48b.3.1.3.1 49 ?2016 integrated device technology, inc. revision 6, july 21, 2016 82p33741 datasheet table 35: sonet/sdh output clock jitter generation (jitter measured on one differential output of apll3 with all other outputs disabled) output frequency rms jitter typ (ps) rm s jitter max (ps) test filter notes 77.76 mhz 0.25 0.28 12 khz to 20 mhz gr-253-core and itu-t g.813 option 2 limit 0.1 ui p-p / 0.01 ui rms (stm-16: 1ui = 0.40 ns) 0.29 1.61 500 hz to 1.3 mhz itu-t g.813 option 1 limit 0.5 ui p-p (stm-1: 1 ui = 6.43 ns) 0.27 0.46 1 khz to 5 mhz itu-t g.813 option 1 limit 0.5 ui p-p (stm-4: 1 ui = 1.61 ns) 0.19 0.21 65 khz to 1.3 mhz itu-t g.813 option 1 limit 0.1 ui p-p (stm-1: 1 ui = 6.43 ns) 0.18 0.21 250 khz to 5 mhz itu-t g.813 option 1 limit 0.1 ui p-p (stm-4: 1 ui = 1.61 ns) 155.52mhz 0.23 0.26 12 khz to 20 mhz gr-253-core and itu-t g.813 option 2 limit 0.1 ui p-p / 0.01 ui rms (stm-16: 1ui = 0.40 ns) 0.29 1.90 500 hz to 1.3 mhz itu-t g.813 option 1 limit 0.5 ui p-p (stm-1: 1 ui = 6.43 ns) 0.27 0.38 1 khz to 5 mhz itu-t g.813 option 1 limit 0.5 ui p-p (stm-4: 1 ui = 1.61 ns) 0.24 0.28 5 khz to 20 mhz itu-t g.813 option 1 limit 0.5 ui p-p (stm-16: 1ui = 0.40 ns) 0.19 0.22 65 khz to 1.3 mhz itu-t g.813 option 1 limit 0.1 ui p-p (stm-1: 1 ui = 6.43 ns) 0.18 0.21 250 khz to 5 mhz itu-t g.813 option 1 limit 0.1 ui p-p (stm-4: 1 ui = 1.61 ns) 0.13 0.15 1 mhz to 20 mhz itu-t g.813 option 1 limit 0.1 ui p-p (stm-16: 1ui = 0.40 ns) 50 ?2016 integrated device technology, inc. revision 6, july 21, 2016 82p33741 datasheet 311.04 mhz 0.23 0.26 12 khz to 20 mhz gr-253-core and itu-t g.813 option 2 limit 0.1 ui p-p / 0.01 ui rms (stm-16: 1ui = 0.40 ns) 0.26 0.30 20khz to 80 mhz gr-253-core and itu-t g.813 option 2 limit 0.3 ui p-p (stm-64: 1 ui = 0.10 ns) itu-t g.813 option 1 limit 0.5 ui p-p (stm-64: 1 ui = 0.10 ns) 0.14 0.19 4 mhz to 80 mhz gr-253-core and itu-t g.813 option 2 limit 0.1 ui p-p (stm-64: 1 ui = 0.10 ns) itu-t g.813 option 1 limit 0.1 ui p-p (stm-64: 1 ui = 0.10 ns) 0.30 1.77 500 hz to 1.3 mhz itu-t g.813 option 1 limit 0.5 ui p-p (stm-1: 1 ui = 6.43 ns) 0.27 0.41 1 khz to 5 mhz itu-t g.813 option 1 limit 0.5 ui p-p (stm-4: 1 ui = 1.61 ns) 0.23 0.27 5 khz to 20 mhz itu-t g.813 option 1 limit 0.5 ui p-p (stm-16: 1ui = 0.40 ns) 0.19 0.22 65 khz to 1.3 mhz itu-t g.813 option 1 limit 0.1 ui p-p (stm-1: 1 ui = 6.43 ns) 0.18 0.21 250 khz to 5 mhz itu-t g.813 option 1 limit 0.1 ui p-p (stm-4: 1 ui = 1.61 ns) 0.11 0.14 1 mhz to 20 mhz itu-t g.813 option 1 limit 0.1 ui p-p (stm-16: 1ui = 0.40 ns) table 35: sonet/sdh output clock jitter generation (jitter measured on one differential output of apll3 with all other outputs disabled) output frequency rms jitter typ (ps) rm s jitter max (ps) test filter notes 51 ?2016 integrated device technology, inc. revision 6, july 21, 2016 82p33741 datasheet 622.08 mhz 0.23 0.26 12 khz to 20 mhz gr-253-core and itu-t g.813 option 2 limit 0.1 ui p-p / 0.01 ui rms (stm-16: 1ui = 0.40 ns) 0.25 0.29 20khz to 80 mhz gr-253-core and itu-t g.813 option 2 limit 0.3 ui p-p (stm-64: 1 ui = 0.10 ns) itu-t g.813 option 1 limit 0.5 ui p-p (stm-64: 1 ui = 0.10 ns) 0.10 0.14 4 mhz to 80 mhz gr-253-core and itu-t g.813 option 2 limit 0.1 ui p-p (stm-64: 1 ui = 0.10 ns) itu-t g.813 option 1 limit 0.1 ui p-p (stm-64: 1 ui = 0.10 ns) 0.30 1.41 500 hz to 1.3 mhz itu-t g.813 option 1 limit 0.5 ui p-p (stm-1: 1 ui = 6.43 ns) 0.28 0.51 1 khz to 5 mhz itu-t g.813 option 1 limit 0.5 ui p-p (stm-4: 1 ui = 1.61 ns) 0.23 0.28 5 khz to 20 mhz itu-t g.813 option 1 limit 0.5 ui p-p (stm-16: 1ui = 0.40 ns) 0.20 0.23 65 khz to 1.3 mhz itu-t g.813 option 1 limit 0.1 ui p-p (stm-1: 1 ui = 6.43 ns) 0.19 0.22 250 khz to 5 mhz itu-t g.813 option 1 limit 0.1 ui p-p (stm-4: 1 ui = 1.61 ns) 0.11 0.13 1 mhz to 20 mhz itu-t g.813 option 1 limit 0.1 ui p-p (stm-16: 1ui = 0.40 ns) note 1: dpll locked to input clock table 35: sonet/sdh output clock jitter generation (jitter measured on one differential output of apll3 with all other outputs disabled) output frequency rms jitter typ (ps) rm s jitter max (ps) test filter notes 52 ?2016 integrated device technology, inc. revision 6, july 21, 2016 82p33741 datasheet table 36: sonet/sdh output clock jitter generation (jitter measured on one differential output of apll1/2 with one differential output enabled) output frequency rms jitter typ (ps) rm s jitter max (ps) test filter notes 19.44 mhz 0.53 0.79 12 khz to 1.3mhz gr-253-core and itu-t g.813 option 2 limit 0.1 ui p-p / 0.01 ui rms (stm-16: 1ui = 0.40 ns) 0.62 0.90 12khz to 5mhz itu-t g.813 option 1 limit 0.5 ui p-p (stm-1: 1 ui = 6.43 ns) 0.85 1.41 500 hz to 1.3 mhz itu-t g.813 option 1 limit 0.5 ui p-p (stm-4: 1 ui = 1.61 ns) 0.86 1.39 1 khz to 5 mhz itu-t g.813 option 1 limit 0.1 ui p-p (stm-1: 1 ui = 6.43 ns) 0.33 0.46 65 khz to 1.3 mhz itu-t g.813 option 1 limit 0.1 ui p-p (stm-4: 1 ui = 1.61 ns) 0.40 0.60 250 khz to 5 mhz itu-t g.813 option 1 limit 0.1 ui p-p (stm-4: 1 ui = 1.61 ns) 77.76 mhz 0.58 1.35 12 khz to 20 mhz gr-253-core and itu-t g.813 option 2 limit 0.1 ui p-p / 0.01 ui rms (stm-16: 1ui = 0.40 ns) 0.87 1.45 500 hz to 1.3 mhz itu-t g.813 option 1 limit 0.5 ui p-p (stm-1: 1 ui = 6.43 ns) 0.82 1.38 1 khz to 5 mhz itu-t g.813 option 1 limit 0.5 ui p-p (stm-4: 1 ui = 1.61 ns) 0.29 0.40 65 khz to 1.3 mhz itu-t g.813 option 1 limit 0.1 ui p-p (stm-1: 1 ui = 6.43 ns) 0.22 0.31 250 khz to 5 mhz itu-t g.813 option 1 limit 0.1 ui p-p (stm-4: 1 ui = 1.61 ns) 53 ?2016 integrated device technology, inc. revision 6, july 21, 2016 82p33741 datasheet 155.52 mhz 0.55 0.82 12 khz to 20 mhz gr-253-core and itu-t g.813 option 2 limit 0.1 ui p-p / 0.01 ui rms (stm-16: 1ui = 0.40 ns) 0.87 1.52 500 hz to 1.3 mhz itu-t g.813 option 1 limit 0.5 ui p-p (stm-1: 1 ui = 6.43 ns) 0.81 1.43 1 khz to 5 mhz itu-t g.813 option 1 limit 0.5 ui p-p (stm-4: 1 ui = 1.61 ns) 0.65 1.03 5 khz to 20 mhz itu-t g.813 option 1 limit 0.5 ui p-p (stm-16: 1ui = 0.40 ns) 0.29 0.41 65 khz to 1.3 mhz itu-t g.813 option 1 limit 0.1 ui p-p (stm-1: 1 ui = 6.43 ns) 0.21 0.30 250 khz to 5 mhz itu-t g.813 option 1 limit 0.1 ui p-p (stm-4: 1 ui = 1.61 ns) 0.20 0.26 1 mhz to 20 mhz itu-t g.813 option 1 limit 0.1 ui p-p (stm-16: 1ui = 0.40 ns) note 1: dpll locked to input clock table 36: sonet/sdh output clock jitter generation (jitter measured on one differential output of apll1/2 with one differential output enabled) output frequency rms jitter typ (ps) rm s jitter max (ps) test filter notes 54 ?2016 integrated device technology, inc. revision 6, july 21, 2016 82p33741 datasheet table 37: sonet/sdh output clock jitter generation (jitter measured on one cmos output of apll1/2 with one cmos output enabled) output frequency rms jitter typ (ps) rm s jitter max (ps) test filter notes 19.44 mhz 0.50 0.75 12 khz to 1.3mhz gr-253-core and itu-t g.813 option 2 limit 0.1 ui p-p / 0.01 ui rms (stm-16: 1ui = 0.40 ns) 0.55 0.78 12khz to 5mhz itu-t g.813 option 1 limit 0.5 ui p-p (stm-1: 1 ui = 6.43 ns) 0.83 2.31 500 hz to 1.3 mhz itu-t g.813 option 1 limit 0.5 ui p-p (stm-4: 1 ui = 1.61 ns) 0.80 2.27 1 khz to 5 mhz itu-t g.813 option 1 limit 0.1 ui p-p (stm-1: 1 ui = 6.43 ns) 0.29 0.54 65 khz to 1.3 mhz itu-t g.813 option 1 limit 0.1 ui p-p (stm-4: 1 ui = 1.61 ns) 0.28 0.40 250 khz to 5 mhz itu-t g.813 option 1 limit 0.1 ui p-p (stm-4: 1 ui = 1.61 ns) 77.76 mhz 0.58 0.91 12 khz to 20 mhz gr-253-core and itu-t g.813 option 2 limit 0.1 ui p-p (stm-4: 1 ui = 1.61 ns) 0.87 2.39 500 hz to 1.3 mhz itu-t g.813 option 1 limit 0.5 ui p-p (stm-1: 1 ui = 6.43 ns) 0.82 2.10 1 khz to 5 mhz itu-t g.813 option 1 limit 0.5 ui p-p (stm-4: 1 ui = 1.61 ns) 0.29 0.42 65 khz to 1.3 mhz itu-t g.813 option 1 limit 0.1 ui p-p (stm-1: 1 ui = 6.43 ns) 0.22 0.37 250 khz to 5 mhz itu-t g.813 option 1 limit 0.1 ui p-p (stm-4: 1 ui = 1.61 ns) note 1: dpll locked to input clock 55 ?2016 integrated device technology, inc. revision 6, july 21, 2016 82p33741 datasheet table 38: dpll1/dpll2 output clock jitter generation (jitter measured on one cmos output of dpll1 /dpll2 with all othe r outputs disabled) output frequency rms jitter typ (ps) rm s jitter max (ps) test filter notes 10 mhz 100.11 619.64 100 hz - 100 khz n x 1.544 mhz (note 2) 100.63 543.45 100 hz - 40 khz 16.06 39.94 8 khz - 40 khz ansi t1.403 limit 0.07 ui p-p (ds1: 1 ui = 647 ns) n x 2.048 mhz (note 3) 99.42 449.83 100 hz - 100 khz 10.66 26.44 18 khz - 100 khz itu-t g.823 limit 0.2 ui p-p (e1: 1 ui = 488 ns) 34.368 mhz 101.67 202.75 100 hz - 800 khz 25.62 39.06 10 khz - 800 khz itu-t g.751 limit 0.05 ui p-p (e3: 1 ui = 29.10 ns) 44.736 mhz 105.16 198.15 100 hz - 400 khz 20.77 27.44 30 khz - 400 khz note 1:dpll1/2 locked to input clock note 2: measured on 12.352 mhz output clock note 3: measured on 16.384 mhz output clock table 39: dpll3 output clock jitter generation (jitter measured on one cmos output of dpll3 with all other outputs disabled) output frequency rms jitter typ (ps) rm s jitter max (ps) test filter notes n x 2.048 mhz note 2 147.325 347.530 100 hz - 100 khz 8.02 17.24 18 khz - 100 khz itu-t g.823 limit 0.2 ui p-p (e1: 1 ui = 488 ns) n x 1.544 mhz note 3 133.88 303.43 100 hz - 40 khz 0.80 1.47 8 khz - 40 khz ansi t1.403 limit 0.07 ui p-p (ds1: 1 ui = 647 ns) note 1:dpll3 locked to input clock note 2: measured on 12.288 mhz output clock note 3: measured on 12.352 mhz output clock 56 ?2016 integrated device technology, inc. revision 6, july 21, 2016 82p33741 datasheet 8.5 input / output clock timing the inputs and outputs are aligned ideally. but due to the circuit delays, there is delay between the inputs and outputs. figure 25. input / output clock timing table 40: input-to-out put delay via apll1/2 output min (ns) max (ns) range (ns pp ) any lvcmos input to any of out01, out02 or out07 13 19 6 (3 around mean) any lvpecl/lvds input to any of out03, out04, out5 or out06 11.5 16.5 5 (2.5 around mean) any input to any apll1/2 output 10 19 9 (4.5 around mean) any input to [m]frsync output 08 8 (typical value is 2.5ns) note 1. the measurements in the above table takes into account any delays in the clock path from any input to any output; throu gh either dpll1 or dpll2 and the either apll1 or apll2. note 2. the measurements in the above table are over operational temperature, varying power supply and repeated power on/off cy cle. note 3. measurements are taken using an ideal ref input and an ideal system clock to account for only internal delays in the de vice. input clock output clock t 1 57 ?2016 integrated device technology, inc. revision 6, july 21, 2016 82p33741 datasheet 8.6 output / output clock timing figure 26. output / output clock timing table 41: apll1/2 output-to-output delay output min (ps) max (ps) output-to-output, lvcmos (out01 to out02) -110 110 output-to-output, lvpecl/lvds (out03 to out04 or out05 to out06) -85 85 output clock output clock t 1 58 ?2016 integrated device technology, inc. revision 6, july 21, 2016 82p33741 datasheet package dimensions figure 27. 144-pin bag package dimensions 59 ?2016 integrated device technology, inc. revision 6, july 21, 2016 82p33741 datasheet figure 28. 144-pin bag package recommended land pattern 60 ?2016 integrated device technology, inc. revision 6, july 21, 2016 82p33741 datasheet ordering information note: "g" after the two-letter pa ckage code denotes pb-free configuration, rohs compliant. while the information presented herein has been checked for both a ccuracy and reliability, integrat ed device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of thir d parties, which would result f rom its use. no other circuits, patents, or licenses are implied. this product is intended for use in norm al commercial applications. any other appli cations such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recomme nded without additional processing by idt. idt does not authorize or warrant any idt product for use in life support devices or critical med ical instruments. revision history table 42: ordering information part/order number package temperature 82P33741BAG 144-pin cabga green package -40 o to +85 o c revision date description of change 2 10/09/14 page 9 3 12/19/14 page 42 3 1/26/14 page 29 3 2/06/15 pages 32, 54 (table 40), 57 (table 42) 3 4/15/15 pages 54, 56-58 3 5/13/15 page 42 4 6/16/15 pages 9, 11, 13, 34 5 3/21/16 page 44 6 7/21 disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the right to modify the products and/or specif ications described herein at any time and at idt?s sole discretion. all information in this document, including descriptions of product features and performance, is subject to change without notice. performance spe cifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. the information co ntained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limi ted to, the suitab ility of idt?s products for any particular purpose, an implied war ranty of merchantability, or non-infringement of the intellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third pa rties. idt?s products are not intended for use in applications involvin g extreme environmental conditions or in life support systems o r similar devices where the failure or malfun ction of an idt product can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their o wn risk, absent an express, written agreement by idt. while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or licenses are implied. this produ ct is intended for use in normal commercial applications. any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recomme nded without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not authorize or warrant any idt product for use in life support devices o r critical medical instruments. integrated device technology, idt and the idt logo are registered trademarks of idt. product specification subject to change wi thout notice. other trademarks and service marks used herein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright ?2016 integrated device technology, inc. all rights reserved. corporate headquarters 6024 silver creek valley road san jose, ca 95138 usa sales 1-800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com tech support email: clocks@idt.com |
Price & Availability of 82P33741BAG
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |